Characterization of Programmable Charge-Trap Transistors (CTTs) in Standard 28-nm CMOS for Nonvolatile Memory and Analog Arithmetic Applications

Abstract

In this article, we characterized the charge trapping and detrapping behaviors of charge-trap transistors (CTTs) in standard 28-nm CMOS technology and formulated its programmable threshold voltage (V TH ). Both thin-oxide and thick-oxide CTT devices are measured, modeled, and analyzed. More than 50-and 100-mV continuous V TH tuning ranges are achieved for thin and thick oxide devices, respectively. Multiple cycles of programming and erasing operations are demonstrated; however, the reliability needs to be solved in the future. To utilize the developed programmable threshold model, a nonvolatile memory (NVM) cell and an analog arithmetic unit (AAU) are proposed and simulated as two proof-of-concept CTT-based designs.INDEX TERMS Analog arithmetic unit (AAU), charge trapping/detrapping, charge-trap transistor (CTT), nonvolatile memory (NVM), programmable threshold voltage.

Quantized Neural Network via Synaptic Segregation Based on Ternary Charge‐Trap Transistors

“…This is considerably less energy compared to an average of 20 µJ consumed for writing and erasing in a commercial silicon‐oxide‐nitride‐oxide‐silicon (SONOS) transistor. [ 38 ]…”