Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation 2018
DOI: 10.1145/3229631.3236091
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Abstract: Improving energy efficiency of the memory subsystem becomes increasingly important for all digital systems due to the rapid growth of data. Many recent schemes have attempted to reduce the DRAM power by relaxing the refresh rate, which may negatively affect the DRAM reliability. To optimize the trade-offs between power and reliability, existing studies rely on experimental setups based on FPGAs and the use of few known data-patterns for exciting rare worst-case circuit reliability effects. However, by doing so…

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