Characterization of HPC workloads on an ARMv8 based server under relaxed DRAM refresh and thermal stress

Mukhanov, Lev; Tovletoglou, Konstantinos; Nikolopoulos, Dimitrios S.; Karakonstantis, Georgios

doi:10.1145/3229631.3236091

Cited by 4 publications

(3 citation statements)

References 21 publications

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“…In the past, there have been several experimental studies that tried to predict the error behavior of DRAM operating under non-nominal circuit parameters [39], such as the refresh period (T REF P ) and the supply voltage (V DD ), and even under various temperatures [19], [27], [39], [52], [53]. However, the main goal of these studies was to improve DRAM performance and energy efficiency by scaling T REF P or V DD [25], [76], rather than model DRAM errors.…”

Section: Introductionmentioning

confidence: 99%

Workload-Aware DRAM Error Prediction using Machine Learning

Mukhanov

Tovletoglou

Vandierendonck

et al. 2019

2019 IEEE International Symposium on Workload Characterization (IISWC)

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The aggressive scaling of technology may have helped to meet the growing demand for higher memory capacity and density, but has also made DRAM cells more prone to errors. Such a reality triggered a lot of interest in modeling DRAM behavior for either predicting the errors in advance or for adjusting DRAM circuit parameters to achieve a better tradeoff between energy efficiency and reliability. Existing modeling efforts may have studied the impact of few operating parameters and temperature on DRAM reliability using custom FPGAs setups, however they neglected the combined effect of workloadspecific features that can be systematically investigated only on a real system.In this paper, we present the results of our study on workloaddependent DRAM error behavior within a real server considering various operating parameters, such as the refresh rate, voltage and temperature. We show that the rate of single-and multi-bit errors may vary across workloads by 8x, indicating that program inherent features can affect DRAM reliability significantly. Based on this observation, we extract 249 features, such as the memory access rate, the rate of cache misses, the memory reuse time and data entropy, from various compute-intensive, caching and analytics benchmarks. We apply several supervised learning methods to construct the DRAM error behavior model for 72 servergrade DRAM chips using the memory operating parameters and extracted program inherent features. Our results show that, with an appropriate choice of program features and supervised learning method, the rate of single-and multi-bit errors can be predicted for a specific DRAM module with an average error of less than 10.5 %, as opposed to the 2.9x estimation error obtained for a conventional workload-unaware error model. Our model enables designers to predict DRAM errors in advance for less than a second and study the impact of any workload and applied software optimizations on DRAM reliability.

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Section: Introductionmentioning

confidence: 99%

Workload-Aware DRAM Error Prediction using Machine Learning

Mukhanov

Tovletoglou

Vandierendonck

et al. 2019

2019 IEEE International Symposium on Workload Characterization (IISWC)

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“…Scaling T REF P and V DD :Many studies [1], [7], [8], [9], [10], [34], [42], [43], [44] tried to improve DRAM performance and energy efficiency by adopting a low refresh period for weak cells. Chang et al [3] provided results of a comprehensive study on reduced-voltage operation in DDR3L memory devices.…”

Section: Related Workmentioning

confidence: 99%

Revealing DRAM Operating GuardBands Through Workload-Aware Error Predictive Modeling

Mukhanov

Tovletoglou

Vandierendonck

et al. 2021

IEEE Trans. Comput.

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Improving the energy efficiency of DRAMs becomes very challenging due to the growing demand for storage capacity and failures induced by the manufacturing process. To protect against failures, vendors adopt conservative margins in the refresh period and supply voltage. Previously, it was shown that these margins are too pessimistic and will become impractical due to high power costs, especially in future DRAM technologies. In this paper, we present a new technique for automatic scaling the DRAM refresh period under reduced supply voltage that minimizes the probability of failures. The main idea behind the proposed approach is that DRAM error behavior is workload-dependent and can be predicted based on particular program inherent features. We use a Machine Learning (ML) method to build a workload-aware DRAM error behavior model based on the program features which we extract from real workloads during our DRAM error characterization campaign. With such a model, we identify the marginal value of the DRAM refresh period under relaxed voltage for each DRAM module of a server that enable us to reduce the DRAM power. We implement a temperature-driven OS governor which automatically sets the module-specific marginal DRAM parameters discovered by the ML model. Our governor reduces the DRAM power by 24% on average while minimizing the probability of failures. Unlike previous studies, our technique: i) does not require intrusive changes to hardware; ii) is implemented on a real server; iii) uses a mechanism that prevents any abnormal DRAM error behavior; iv) can be easily deployed in data centers.

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“…We build a DRAM error model that considers not only the DRAM temperature and the refresh period, as prior works [7], [20], but also workload specific features. Such a model allows us to distinguish the DRAM reliability behavior based on the different traces that can be simulated in CloudSim (and which provide information about access rates and memory footprint), while considering recent findings that show that DRAM errors are workload-dependent and may vary by 8x across workloads [21]. Formally, our model predicts a target DRAM error metric (i.e.…”

Section: A Dram Error Modelingmentioning

confidence: 99%

Increasing the Profit of Cloud Providers through DRAM Operation at Reduced Margins

Kalogirou

Antonopoulos

Bellas

et al. 2020

2020 20th IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing (CCGRID)

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Energy reduction is a key objective in cloud computing, with DRAM memories being responsible for a significant portion of the energy consumption of data center nodes. Improving DRAM energy efficiency is challenging, mainly due to the increased manufacturing variability inherent in DRAM production. As a protection against variability induced faults, vendors prefer to adopt very conservative margins for DRAM operating parameters, such as the refresh rate and supply voltage, in order to guarantee correct operation even in the worst process variation and operating conditions. In this paper, we investigate the exploitation of DRAM margins to improve energy efficiency in data center nodes. Any non-judicious relaxation of these parameters may result in DRAM errors which may, in turn, violate the service level agreement (SLA) between the provider and the customer, thus triggering penalties. We introduce a model that captures the most important aspects of job management and system configuration. We also introduce RM-DRAM, a scheduling and node configuration policy that exploits the extended margins of DRAMs to reduce the operator cost by considering the trade-off between the cost of energy consumption and potential SLA violations. RM-DRAM also employs cost-aware (rather than threshold-based) VM consolidation. We extract the parameters used in the simulation (particularly power consumption and error rates) through characterization of a commercial ARMbased server. We perform simulations to evaluate the effectiveness of our approach and show that significant gains, up to 34.84% and 29.53% in energy and cost, respectively, can be achieved compared with a state-of-the-art policy.

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Characterization of HPC workloads on an ARMv8 based server under relaxed DRAM refresh and thermal stress

Cited by 4 publications

References 21 publications

Workload-Aware DRAM Error Prediction using Machine Learning

Workload-Aware DRAM Error Prediction using Machine Learning

Revealing DRAM Operating GuardBands Through Workload-Aware Error Predictive Modeling

Increasing the Profit of Cloud Providers through DRAM Operation at Reduced Margins

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