Characterization of an Oxide Trap Leading to Random Telegraph Noise in Gate-Induced Drain Leakage Current of DRAM Cell Transistors

Oh, Byoungchan; Cho, Heung-Jae; Kim, Heesang; Son, Younghwan; Kang, Taewook; Park, Sunyoung; Jang, Seunghyun; Lee, Jong-Ho; Shin, Hyungcheol

doi:10.1109/ted.2011.2126046

Cited by 26 publications

(2 citation statements)

References 20 publications

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“…Conventionally, border traps are investigated using Multi-Frequency Charge Pumping (CP) technique [7]. Unlike bulk-Si FETs, devices with InGaAs channel are usually grown on insulating substrate and thus only have three terminals, making the CP impossible to be applied.…”

Section: Introductionmentioning

confidence: 99%

An Investigation on Border Traps in III–V MOSFETs With an In_0.53Ga_0.47As Channel

Zhang

Franco

et al. 2015

IEEE Trans. Electron Devices

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Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristic are poorly understood at present. In this work, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origin. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modelling and device time-to-failure projection.

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Section: Introductionmentioning

confidence: 99%

An Investigation on Border Traps in III–V MOSFETs With an In_0.53Ga_0.47As Channel

Zhang

Franco

et al. 2015

IEEE Trans. Electron Devices

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“…The RTN amplitude in GIDL current have been studied but only in the BBT regime [5]. Because of the smaller applied voltage in current DRAM devices, the TAT mechanism would be more dominant in the GIDL current of the DRAM devices.…”

Section: Introductionmentioning

confidence: 99%

Analysis and modeling for random telegraph noise of GIDL current in saddle MOSFET for DRAM application

Moon

Lee

Shin

et al. 2014

IEICE Electron. Express

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AVERT: An elaborate model for simulating variable retention time in DRAMs

Kim

Cha

Milor

2015

Microelectronics Reliability

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Characterization of an Oxide Trap Leading to Random Telegraph Noise in Gate-Induced Drain Leakage Current of DRAM Cell Transistors

Cited by 26 publications

References 20 publications

An Investigation on Border Traps in III–V MOSFETs With an In_0.53Ga_0.47As Channel

An Investigation on Border Traps in III–V MOSFETs With an In_0.53Ga_0.47As Channel

Analysis and modeling for random telegraph noise of GIDL current in saddle MOSFET for DRAM application

AVERT: An elaborate model for simulating variable retention time in DRAMs

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Characterization of an Oxide Trap Leading to Random Telegraph Noise in Gate-Induced Drain Leakage Current of DRAM Cell Transistors

Cited by 26 publications

References 20 publications

An Investigation on Border Traps in III–V MOSFETs With an In0.53Ga0.47As Channel

An Investigation on Border Traps in III–V MOSFETs With an In0.53Ga0.47As Channel

Analysis and modeling for random telegraph noise of GIDL current in saddle MOSFET for DRAM application

AVERT: An elaborate model for simulating variable retention time in DRAMs

Contact Info

Product

Resources

About

An Investigation on Border Traps in III–V MOSFETs With an In_0.53Ga_0.47As Channel

An Investigation on Border Traps in III–V MOSFETs With an In_0.53Ga_0.47As Channel