2015 Symposium on VLSI Technology (VLSI Technology) 2015
DOI: 10.1109/vlsit.2015.7223639
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Challenges for high-density 16Gb ReRAM with 27nm technology

Abstract: Enabling a high-density ReRAM product requires: developing a cell that meets a stringent bit error rate, BER, at low program current, integrating the cell without material damage, and providing a high-drive selector at scaled nodes. We discuss ReRAM performance under these constraints and present a 16Gb, 27nm ReRAM capable of 10 5 cycles with BER < 7x10 -5 .

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Cited by 10 publications
(8 citation statements)
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“…In particular, storage class memories (SCM) can be envisaged where the RRAM would be placed between the DRAM and storage memory in the hierarchy due to its high speed and good endurance. A few years ago, Micron presented a 16 Gb RRAM in a 27 nm node targeting SCM applications with excellent reliability, achieving 10 5 cycles with <7 × 10 −5 of bit error rate due to optimized programming schemes [68]. No further work has reported from Micron but SONY also provides cross-point RRAM for storage class memory applications with an excellent widow margin of two decades at 3δ [69].…”
Section: Filamentary Memorymentioning
confidence: 99%
“…In particular, storage class memories (SCM) can be envisaged where the RRAM would be placed between the DRAM and storage memory in the hierarchy due to its high speed and good endurance. A few years ago, Micron presented a 16 Gb RRAM in a 27 nm node targeting SCM applications with excellent reliability, achieving 10 5 cycles with <7 × 10 −5 of bit error rate due to optimized programming schemes [68]. No further work has reported from Micron but SONY also provides cross-point RRAM for storage class memory applications with an excellent widow margin of two decades at 3δ [69].…”
Section: Filamentary Memorymentioning
confidence: 99%
“…[16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32] Their integration into practical memory chips has continued to advance and a 16 Gbit memory chip was reported with write and read speeds of 180 MB s −1 and 900 MB s −1 , respectively. 33) However, while the fundamental operating mechanism can be explained based on the electrochemical reaction, [16][17][18] the cyclic resistance switching and device degradation mechanisms have not yet been fully understood. While there are some examples of commercialized ReRAM chips, a lack of knowledge of the switching mechanism limits its mass production and application.…”
Section: Introductionmentioning
confidence: 99%
“…Emerging memories such as magnetic random access memory, [1][2][3][4][5] resistive random access memory, [6][7][8][9][10][11][12] ferroelectric random access memory, [13][14][15][16] phase change memory, [17][18][19][20][21][22] and ionic memory [23][24][25] are receiving much attention due to their non-volatility, simple structure, scalability, low power consumption, and high-speed operation. Also, emerging memories are expected to be used for various applications such as storage-class memories, [26][27][28][29][30] embedded memories for microcontrollers unit, 31,32) system on a chip, 32,33) and in-memory computing 34,35) for neuromorphic applications. 36,37) Although the physical operation principles of emerging memories are different from each other, the resistance modification is commonly used for the memory operation.…”
Section: Introductionmentioning
confidence: 99%