CELLERITY: A Fully Automatic Layout Synthesis System For Standard Cell Libraries

Guruswamy, Mohan; Maziasz, Robert L.; Dulitz, Daniel; Raman, Shanmuganathan; Chiluvuri, V.K.R.; Fernández, Andrea Fernández; Jones, Larry G.

doi:10.1109/dac.1997.597167

Cited by 24 publications

(23 citation statements)

References 18 publications

(4 reference statements)

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“…The synthesis of cell libraries has been one of the targets for design automation since long ago [2,3]. With large feature dimensions, the layout elements could be placed with very simple design rules.…”

Section: A Cell Synthesismentioning

confidence: 99%

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A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing

Cortadella

Petit

Fernandez

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-An approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core contribution is a detailed-routing algorithm based on a Boolean formulation of the problem. The algorithm uses a novel encoding scheme, graph theory to support floating terminals, efficient heuristics to reduce the computational cost and minimization of the number of unconnected pins in case the cell is unroutable. The versatility of the algorithm is demonstrated by routing single-and doubleheight cells. The efficiency is ascertained by synthesizing a library with 127 cells in about one hour and a half of CPU time. The layouts derived by the implemented tool have also been compared with the ones from a commercial library, thus showing the competitiveness of the approach for gridded geometries.

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Section: A Cell Synthesismentioning

confidence: 99%

“…For standard cells, in which area is limited by the cell height, compaction was often integrated to optimize area [3].…”

Section: Cell Routingmentioning

confidence: 99%

A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing

Cortadella

Petit

Fernandez

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…We will refer to this as pin-to-wire routing. One such motivation is to enable routing by abutment, in the manner that standard cell-based ASICs connect power rails in rows of cells [2], or that a datapath layout generator might abut stages in a layout [3]. In the FPGA context, this idea translates to having preplaced and pre-routed modules that could connect together by abutment, presuming efficient routing to and from specific wire segments in an FPGA routing channel is possible.…”

Section: Introductionmentioning

confidence: 99%

On the difficulty of pin-to-wire routing in FPGAs

Shah

Rose

2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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While FPGA programmable routing networks are designed to connect logic block output pins to input pins, FPGA users and architects sometimes become motivated to create connections between pins and specific wires in an FPGA. We call these pin-to-wire connections, and they are motivated by several reasons: first, a desire to employ routing-by-abutment, as commonly done in custom VLSI, to build modular, pre-laid out systems. Second, partial reconfiguration of FPGAs often requires that circuits in the FPGA connect by abutment. Third, pin-to-wire routing is required to make use of resources that reside within the routing network itself, such as the plentiful multiplexers in the network, or even the configuration bits themselves. In this paper we attempt to understand and measure how difficult it is to form such pin-to-wire connections. We show, for example, under an experimental scenario close to routing-by-abutment, that the total routed wirelength compared to a flat placement of the complete system increases by about 6%, that the critical path delay increases by 15% and the router effort goes up by a factor of 3.5. To achieve this result, it is important to be careful in selecting the specific target wires. Overall we demonstrate that while pin-to-wire connections definitely impose increased stress on the routing architecture and router, it is possible to route some reasonable number of them, and so they can be used under some circumstances.

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“…The recent significant progress in automated cell-layout generation [1][2] has made transistorlevel optimization a feasible and practical solution. The latest researches have demonstrated that such optimization techniques could be successfully applied to real design projects and achieved significant performance improvements [3] [4].…”

Section: Introductionmentioning

confidence: 99%

An algebraic approach for transistor circuit synthesis

Yoshida

Ikeda

Asada

2005

2005 12th IEEE International Conference on Electronics, Circuits and Systems

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This paper presents an algebraic approach for transistor circuit synthesis. Our approach relies on a graph structure which encodes multiple circuit structural configurations. The proposed procedure implicitly enumerates possible circuit configurations via algebraic transformations in the graph structure, and efficiently finds a minimum solution among them. Experimental results on a benchmark suite targeting standard cell implementations show that the proposed procedure generated smaller transistor circuits than a technology mapping based approach in a comparable runtime.

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CELLERITY: A Fully Automatic Layout Synthesis System For Standard Cell Libraries

Cited by 24 publications

References 18 publications

A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing

A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing

On the difficulty of pin-to-wire routing in FPGAs

An algebraic approach for transistor circuit synthesis

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