Cause of erase speed degradation during two-bit per cell operation of a trapping nitride storage flash memory cell

Tsai, Wen-Jer; Zous, N.K.; Chou, Ming Yueh; Huang, Shih-Che; Chen, H.Y.; Yeh, Yun-Tien; Liu, M.Y.; Yeh, Chih-Ting; Wang, T.; Ku, Jui Tai; Lu, Chih‐Yuan

doi:10.1109/relphy.2004.1315383

Cited by 8 publications

(2 citation statements)

References 12 publications

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“…1, we plot the required erase time for the entire sector to pass erase-verify. The increase of erase time with cycle number is due to the location mismatch of injected electrons and holes [6]. In order to compensate for stored electrons far in the channel region, more hole injection is needed in erase operation.…”

Section: Methodsmentioning

confidence: 99%

Lateral Migration of Trapped Holes in a Nitride Storage Flash Memory Cell and Its Qualification Methodology

Zous

Lee

Tsai

et al. 2004

IEEE Electron Device Lett.

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Abstract-The negative threshold voltage ( ) shift of a nitride storage flash memory cell in the erase state will result in an increase in leakage current. By utilizing a charge pumping method, we found that trapped hole lateral migration is responsible for this shift. Hole transport in nitride is characterized by monitoring gate induced drain leakage current and using a thermionic emission model. The hole emission induced shift shows a linear correlation with bake time in a semi-logarithm plot and its slope depends on the bake temperature. Based on the result, an accelerated qualification method for the negative drift is proposed.

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Section: Methodsmentioning

confidence: 99%

Lateral Migration of Trapped Holes in a Nitride Storage Flash Memory Cell and Its Qualification Methodology

Zous

Lee

Tsai

et al. 2004

IEEE Electron Device Lett.

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“…A very little mismatch exists between the initial and erased I D -V G curves. This mismatch may be attributed to the difference between programming and erasing carrier injection sites and distributions [14].…”

Section: B Disturbance Cycling Endurance and Charge Retentionmentioning

confidence: 99%

Performance Improvement and Scalability of Nonoverlapped Implantation nMOSFETs With Charge-Trapping Spacers as Nonvolatile Memories

Jeng

Chia-Sung

Hon

et al. 2007

IEEE Trans. Electron Devices

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This paper explores gate-to-source/drain nonoverlapped implantation (NOI) devices that function as nonvolatile memories (NVMs) by trapping charges in the silicon nitride spacers. These NOI nMOSFET devices with improved NVM characteristics were simulated and demonstrated. For a 0.8 V shift in the threshold voltage, the programming and erasing speeds of NOI devices are as fast as 40 and 60 µs, respectively. Improvements of other related NVM characteristics, including charge retention and cycling endurance, are reported. Finally, the scalability of NOI devices is simulated and discussed. Index Terms-Charge trapping, nonoverlapped implantation (NOI), nonvolatile memory (NVM). Since 2005, he has beenan Associate Professor in the Department of Electronic Engineering, Chung Yuan Christian University with conducting research on surface acoustic wave sensors and semiconductor memories. His current research interests are in the areas of advanced CMOS processing technologies; characterization, simulation and modeling of deep-submicrometer nonvolatile memory devices and the cell array design for nonvolatile memory applications.

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A highly punchthrough-immune operation method for an ultra-short-channel hot-carrier-injection type non-volatile memory cell

Tsai

Huang

et al. 2008

2008 IEEE International Electron Devices Meeting

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Cause of erase speed degradation during two-bit per cell operation of a trapping nitride storage flash memory cell

Cited by 8 publications

References 12 publications

Lateral Migration of Trapped Holes in a Nitride Storage Flash Memory Cell and Its Qualification Methodology

Lateral Migration of Trapped Holes in a Nitride Storage Flash Memory Cell and Its Qualification Methodology

Performance Improvement and Scalability of Nonoverlapped Implantation nMOSFETs With Charge-Trapping Spacers as Nonvolatile Memories

A highly punchthrough-immune operation method for an ultra-short-channel hot-carrier-injection type non-volatile memory cell

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