Cardio: Adaptive CMPs for reliability through dynamic introspective operation

Pellegrini, Andrea; Bertacco, Valeria

doi:10.1109/hldvt.2011.6113983

Cited by 5 publications

(1 citation statement)

References 41 publications

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“…This solution requires limited engineering effort and does not significantly hinder either the performance or the power budget of fault-free systems. However, because a single fault can disable large portions of the design, this technique does not scale well to higher fault rates [24].…”

Section: Introductionmentioning

confidence: 99%

Viper: Virtual pipelines for enhanced reliability

Pellegrini¹,

Greathouse²,

Bertacco³

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device reliability is a secondary concern. As the rate of permanent hardware faults increases, robustness will become a first class constraint for even low-cost systems. Current research into reliable architectures has focused on ad-hoc solutions to improve designs without altering their centralized control logic. Unfortunately, this centralized control presents a single point of failure, which limits long-term robustness.To address this issue, we introduce Viper, an architecture built from a redundant collection of fine-grained hardware components. Instructions are perceived as customers that require a sequence of services in order to properly execute. The hardware components vie to perform what services they can, dynamically forming virtual pipelines that avoid defective hardware. This is done using distributed control logic, which avoids a single point of failure by construction.Viper can tolerate a high number of permanent faults due to its inherent redundancy. As fault counts increase, its performance degrades more gracefully than traditional centralized-logic architectures. We estimate that fault rates higher than one permanent faults per 12 million transistors, on average, cause the throughput of a classic CMP design to fall below that of a Viper design of similar size.

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Section: Introductionmentioning

confidence: 99%