Bus Energy Consumption for Multilevel Signals

Rokhani, Fakhrul Zaman; Sobelman, Gerald E.

doi:10.1109/tcsi.2009.2016177

Cited by 9 publications

(3 citation statements)

References 31 publications

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“…The power consumption considered in the analysis can be given by

P = P_{encoder} + P_{link} + P_{decoder}

where P encoder and P decoder are extracted from the synthesis power results using Synopsys Design Compiler with 800 MHz target frequency. On the other hand, link power ( P link ) is evaluated using [54, 55]

P_{link} = ()(, L \cdot C_{L} \cdot α_{wire} + ()(, L - 1) \cdot C_{C} \cdot α_{C}) \cdot \frac{1}{2} \cdot V^{2} \cdot f

where L represents the number of wires in the link;

C_{L}

is the wire self‐capacitance;

C_{C}

is the coupling capacitance between wires;

α_{wire}

is the wire self‐transition activity factor;

α_{C}

is the wire coupling transition activity factor; V is the supply voltage; and f is the clock frequency. It should be noted that the effective coupling capacitance is reduced for duplication‐based schemes from

false(L - 1 false) \cdot C_{C}

()(, ()(, L / 2) - 1) \cdot C_{C}

.…”

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Multi‐bit error control coding with limited correction for high‐performance and energy‐efficient network on chip

Flayyih

Samsudin

Hashim

et al. 2019

IET Circuits, Devices & Systems

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In the presence of deep submicron noise, providing reliable and energy-efficient network on-chip operation is becoming a challenging objective. In this study, the authors propose a hybrid automatic repeat request (HARQ)-based coding scheme that simultaneously reduces the crosstalk induced bus delay and provides multi-bit error protection while achieving high-energy savings. This is achieved by calculating two-dimensional parities and duplicating all the bits, which provide single error correction and six errors detection. The error correction reduces the performance degradation caused by retransmissions, which when combined with voltage swing reduction, due to its high error detection, high-energy savings are achieved. The results show that the proposed scheme reduces the energy consumption up to 51.7% as compared with other schemes while achieving the target link reliability level. Also, it shows improved network performance as compared with ARQ-based scheme and close to forward error correction-based schemes.

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“…The power consumption considered in the analysis can be given by

P = P_{encoder} + P_{link} + P_{decoder}

P_{link} = ()(, L \cdot C_{L} \cdot α_{wire} + ()(, L - 1) \cdot C_{C} \cdot α_{C}) \cdot \frac{1}{2} \cdot V^{2} \cdot f

where L represents the number of wires in the link;

C_{L}

is the wire self‐capacitance;

C_{C}

is the coupling capacitance between wires;

α_{wire}

is the wire self‐transition activity factor;

α_{C}

false(L - 1 false) \cdot C_{C}

()(, ()(, L / 2) - 1) \cdot C_{C}

.…”

Section: Resultsmentioning

confidence: 99%

“…The power consumption considered in the analysis can be given by P = P encoder + P link + P decoder (17) where P encoder and P decoder are extracted from the synthesis power results using Synopsys Design Compiler with 800 MHz target frequency. On the other hand, link power (P link ) is evaluated using [54,55]…”

Section: Power Consumptionmentioning

confidence: 99%

Multi‐bit error control coding with limited correction for high‐performance and energy‐efficient network on chip

Flayyih

Samsudin

Hashim

et al. 2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…By utilizing ternary logic in design of digital systems, energy efficiency and simplicity can be achieved due to the reduced interconnect complexity as well as the chip area [30], therefore resulting in smaller power delay [31]. In addition, the transmission channels can be better utilized due to the higher storage density of each line.…”

Section: Circuit Level Implementation Of Ternary Logicmentioning

confidence: 99%

Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits

et al. 2021

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The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility.

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Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus

Ching

Boon

Yeong

et al. 2010

2010 IEEE Asia Pacific Conference on Circuits and Systems

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In this paper, the technique of optimal interconnects width and spacing is analyzed to reduce the area, delay and area-delay-product of multi-level signaling on-chip bus. To capture the delay impact from cross-coupling capacitance in the deep sub-micron on-chip bus, the Miller Capacitance Factor (MCF) for 4-level signals is developed. Results show that our proposed technique reveals the trade-off between bus area and delay to achieve the optimized bus configuration.

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Bus Energy Consumption for Multilevel Signals

Cited by 9 publications

References 31 publications

Multi‐bit error control coding with limited correction for high‐performance and energy‐efficient network on chip

Multi‐bit error control coding with limited correction for high‐performance and energy‐efficient network on chip

Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits

Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus

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