Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs

Indrusiak, Leandro Soares; Burns, Alan; Nikolic, Borislav

doi:10.23919/date.2018.8342006

Cited by 20 publications

(59 citation statements)

References 11 publications

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“…Nonetheless, for the sake of completeness of this work, we will compare our approach against both SOT A and SOT A + . A more detailed explanation of these methods is given in Section 5, and for further details the reviewer is advised to consult the work of Indrusiak et al (2018).…”

Section: Related Workmentioning

confidence: 99%

Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays

et al. 2018

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Nowadays available multiprocessor platforms predominantly use a Network-on-Chip (NoC) architecture as an interconnect medium, due to its good scalability and performance. During the last decade, NoCs received a significant amount of attention from the real-time community. One promising category of approaches suggests to employ already existing hardware features called virtual channels, and dedicate them, exclusively, to individual communication traffic flows. In this way, NoCs become more amenable to the real-time analysis, which is an essential requirement for providing both safe and tight worst-case analysis methods, and consequently deriving real-time guarantees. In this manuscript, we present the approach which falls in the aforementioned category. Specifically, we propose a novel method for the worst-case analysis of the NoC traffic, assuming the existence of per-flow dedicated virtual channels. Compared to the state-of-the-art techniques, our approach yields substantially tighter upper-bounds on the worst-case traversal times (WCTTs) of communication traffic flows. By employing the proposed method, resource over-provisioning can be mitigated to a large extent, and significant designcost reductions can be achieved. Moreover, we implemented a cycle-accurate simulator of the assumed NoC architecture, and used it to assess the tightness of derived WCTT bounds. Finally, we reached an interesting conclusion that bigger virtual channel buffers do not necessarily lead to better results, and in many cases can be counter-productive, which is a very important finding for system designers.

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Section: Related Workmentioning

confidence: 99%

Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays

et al. 2018

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“…The communication between the cores and the router is made by two unidirectional links (one from c to r and other from r to c). In this work, we have applied the widely used 2D-mesh topology [2][8] [9], considering wormhole NoCs with priority-preemptive arbitration, widely studied in the literature due to their ability to provide resources for hard real-time guarantees [9] [16].…”

Section: Performance Analysis For Nocsmentioning

confidence: 99%

“…In this paper, we have applied the endto-end schedulability analysis presented in [8], which ensures all tasks executing over a processing core and their respective packets low over a NoC will meet their deadlines even in the worst-case scenario. For the analysis of packet lows, we incorporated the improvements from [9], which consider the impact of inite bufers, low control backpressure, and multi-point progressive blocking in priority-preemptive NoCs. For a comprehensive review on NoC performance analysis, see [10].…”

Section: Performance Analysis For Nocsmentioning

confidence: 99%

“…The platform follows the architecture stated in section 2, with homogeneous cores running priority-preemptive task schedulers, 2D-mesh NoC interconnected with XY squared dimension routing, distributed memory, 8 virtual channels with priority-preemptive link arbitration. The schedulability analysis is based on [8] and [9], and the results are presented in Fig. 6.…”

Section: Experimental Setup and Related Workmentioning

confidence: 99%

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Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms

Penny

Palomino

Porto

et al. 2019

Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design

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Today, several applications running into embedded systems have to fulill soft or hard timing constraints. Video applications, like the modern High Eiciency Video Coding (HEVC), e.g., most often have soft real-time constraints. However, in speciic scenarios, such as in robotic surgeries, the coupling of satellites and so on, harder timing constraints arise, becoming a huge challenge. Although the implementation of such applications in Networks-on-Chip (NoCs) being an alternative to reduce their algorithmic complexity and meet real-time constraints, a performance evaluation of the mapped NoC and the schedulability analysis for a given application are mandatory. In this work we make a performance evaluation of HEVC Residual Coding Loop (RCL) mapped onto a NoC-based embedded platform, considering the encoding of a single 1920x1080 pixels frame. A set of analysis exploring the combination of diferent NoC sizes and task mapping strategies were performed, showing for the typical and upper-bound workload cases scenarios when the application is schedulable and meets the real-time constraints. CCS CONCEPTS • Information systems → Multimedia information systems; • Networks → Network on chip; • Computer systems organization → Real-time systems; Embedded systems.

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“…More recently, authors in [45] have shown that the model proposed in [37] and later enhanced [16] has some deficiencies. Based on the findings in [45], authors in [14] have proposed a tight alternative model for prioritypreemptive real-time networks. Best-effort wormhole NoCs can also be employed in the context of hard-real time systems by deriving latency upperbounds as described in [31].…”

Section: Related Workmentioning

confidence: 99%

NoCo: ILP-Based Worst-Case Contention Estimation for Mesh Real-Time Manycores

Cardona

Hernández

Mezzetti

et al. 2018

2018 IEEE Real-Time Systems Symposium (RTSS)

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Manycores are capable of providing the computational demands required by functionally-advanced critical applications in domains such as automotive and avionics. In manycores a network-on-chip (NoC) provides access to shared caches and memories and hence concentrates most of the contention that tasks suffer, with effects on the worst-case contention delay (WCD) of packets and tasks' WCET. While several proposals minimize the impact of individual NoC parameters on WCD, e.g. mapping and routing, there are strong dependences among these NoC parameters. Hence, finding the optimal NoC configurations requires optimizing all parameters simultaneously, which represents a multidimensional optimization problem. In this paper we propose NoCo, a novel approach that combines ILP and stochastic optimization to find NoC configurations in terms of packet routing, application mapping, and arbitration weight allocation. Our results show that NoCo improves other techniques that optimize a subset of NoC parameters.

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Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs

Cited by 20 publications

References 11 publications

Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays

Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays

Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms

NoCo: ILP-Based Worst-Case Contention Estimation for Mesh Real-Time Manycores

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