2017
DOI: 10.1186/s11671-017-2189-3
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Breaking Through the Multi-Mesa-Channel Width Limited of Normally Off GaN HEMTs Through Modulation of the Via-Hole-Length

Abstract: We present new normally off GaN high-electron-mobility transistors (HEMTs) that overcome the typical limitations in multi-mesa-channel (MMC) width through modulation of the via-hole-length to regulate the charge neutrality screen effect. We have prepared enhancement-mode (E-mode) GaN HEMTs having widths of up to 300 nm, based on an enhanced surface pinning effect. E-mode GaN HEMTs having MMC structures and widths as well as via-hole-lengths of 100 nm/2 μm and 300 nm/6 μm, respectively, exhibited positive thres… Show more

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Cited by 5 publications
(2 citation statements)
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“…In the case of the NC-HEMTs, the I DMAX (W NC ) with the gate annealing treatment (400 • C) rose to 785 mA mm −1 (800 nm), 720 mA mm −1 (600 nm), 625 mA mm −1 (400 nm), and 470 mA mm −1 (200 nm). Generally, increasing the etching area reduces the maximum drain current due to a reduction in the sheet carrier density [50]. After the gate annealing treatment, the incremental increases in electron saturation velocity (⃗ v ), as shown in figure 4(c), caused the peak transconductance and I DMAX to increase significantly [48].…”
Section: Resultsmentioning
confidence: 99%
“…In the case of the NC-HEMTs, the I DMAX (W NC ) with the gate annealing treatment (400 • C) rose to 785 mA mm −1 (800 nm), 720 mA mm −1 (600 nm), 625 mA mm −1 (400 nm), and 470 mA mm −1 (200 nm). Generally, increasing the etching area reduces the maximum drain current due to a reduction in the sheet carrier density [50]. After the gate annealing treatment, the incremental increases in electron saturation velocity (⃗ v ), as shown in figure 4(c), caused the peak transconductance and I DMAX to increase significantly [48].…”
Section: Resultsmentioning
confidence: 99%
“…Recently, fin-shaped tri-gate structures, formed by structuring parts of the gate region [10], have been developed to demonstrate high-voltage GaN MOS-HEMTs with superior gate control, leading to large ON-OFF ratios and small subthreshold slopes (SS), along with much reduced leakage current, and significantly increased breakdown voltages [15]- [17]. In addition, an excellent control of the threshold voltage (V TH ) in tri-gates, achieved by changing the fin width (w), offers an additional device design tool [17] and has been explored to reach E-mode operation in previous works [18]- [21]. This approach relies only on one lithography step to achieve positive threshold voltage through strain relaxation of the barrier layer and electron depletion from the fin sidewalls, and does not require any critical etching as for gate recess or p-GaN gates.…”
Section: Introductionmentioning
confidence: 99%