Bias Voltage DAC Operating at Cryogenic Temperatures for Solid-State Qubit Applications

Vliex, P.; Degenhardt, C.; Grewing, Christian; Kruth, A.; Nielinger, Dennis; Waasen, S. van; Heinen, Stefan

doi:10.1109/lssc.2020.3011576

Cited by 14 publications

(6 citation statements)

References 7 publications

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“…The power consumption of the DAC is 5.8 µW at a sampling rate of 3.9 kHz. Since the power consumption of the charge redistribution DAC highly depends on the sampling rate, the power was measured at the same frequency as the refresh rate of the other charge redistribution type [20] for a fair comparison. The breakdown of power consumption is 5.7 µW for digital circuit (0.9 V), 0.1 µW for analog circuit (2.5 V), and 20 nW for charging and discharging the capacitors.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…However, non-negligible current constantly flows, resulting in the waste of power dissipation in this bias voltage generator even during static operation [19]. A capacitive DAC operating at cryogenic temperature has also been presented [20]. Its quiescent current is very small, however, it requires multiple intermediate voltages to calibrate capacitor mismatches.…”

Section: Introductionmentioning

confidence: 99%

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An 11-bit 0.008mm<sup>2</sup> charge-redistribution digital-to-analog converter operating at cryogenic temperature for large-scale qubit arrays

Miki

Takahashi

Nagata

2022

IEICE Electron. Express

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This letter presents a cryogenic digital-to-analog converter (DAC) for controlling qubits in a large-scale quantum computer. The capacitor arrays composing a charge-redistribution DAC are miniaturized by effectively utilizing the cryogenic characteristics of extremely low noise and leakage. Furthermore, capacitor mismatches due to their small size are automatically corrected by a newly proposed calibration technique with a small area-overhead. Fabricated in 40 nm CMOS and measured at cryogenic temperature, the prototype 11-bit DAC achieved a very small area of 0.3 mm 2 and low power consumption of 5.8 µW, while realizing a non-linearity error within +/-2 LSB.

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Section: Measurement Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An 11-bit 0.008mm<sup>2</sup> charge-redistribution digital-to-analog converter operating at cryogenic temperature for large-scale qubit arrays

Miki

Takahashi

Nagata

2022

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…where the best values for the fitting parameters are These results indicate that the allowable operating voltage window is of the order of 0.1 V, which can be achieved by cryogenic CMOS circuit systems, 40,41) and is essential for controlling scalable integrated QD arrays. 23) We also evaluated the stability and accuracy of the SEP for about 1 h by periodically switching the input RF signal to reduce the time-dependent current fluctuation in the measurement setup, as shown in Fig.…”

Section: Demonstration Of Sep On a Qd Arraymentioning

confidence: 89%

Single-electron pump in a quantum dot array for silicon quantum computers

Utsugi

Lee

Tsuchiya

et al. 2023

Jpn. J. Appl. Phys.

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It is necessary to load single electrons into individual quantum dots (QDs) in an array for implementing fully scalable silicon-based quantum computers. However, this single-electron loading would be impacted by the variability of the QD characteristics, and suppressing this variability is highly challenging even in the state-of-the-art silicon front-end process. Here, we used a single-electron pump (SEP) for loading single electrons into a QD array as a preparation step to use electrons as spin qubits. We used parallel gates in the QD array as a SEP and demonstrated 100-MHz operation with an accuracy of 99% at 4 K. By controlling the timing of a subsequent gate synchronously as a shutter, we found that the jitter representing electron transfer was less than 10 ns, which would be acceptable for a typical operation speed of around 1 MHz for silicon qubits.

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“…But as the number of quantum bits grows, controllers at room temperature cannot meet the demand for controlling large-scale quantum processors. So integrated circuit controllers based on cryogenic CMOS (Cryo-CMOS) circuits operating at temperatures below 4 Kelvin are proposed [11][12][13][14]. Controller circuits operating at ultra-low temperatures can provide larger system-on-a-chip integration to support higher ultra-low temperatures can provide larger system-on-a-chip integration to support higher numbers of quantum bits, significantly reducing the connection between low-temperature and room-temperature electronics.…”

Section: Introductionmentioning

confidence: 99%

A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers

Xin

Lai

et al. 2023

Electronics

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This paper analyzes the performance requirements that need to be met by a clock generator applied to a low-temperature quantum computer and analyzes the negative effects on the clock generator circuit under low-temperature conditions. In order to meet the performance requirements proposed in this paper and suppress the negative effects brought about by the low temperature, a clock generator for ultra-low-temperature quantum computing is designed. This clock generator is designed by using F-CLASS Voltage Controlled Oscillator (VCO), power filter, tail resistor, differential charge pump, and other techniques. And the noise characteristics of the clock generator are analyzed by Impulse Sensitive Function (ISF) and simulation results. After simulation tests, the average power consumption of the clock generator designed in this paper is 7 mW, the phase noise is −121 dBc/Hz@1 MHz, and the jitter is 62 fs. The performance of the clock generator meets the performance requirements proposed in this paper, and the reduction in the corner frequency proves that the circuit will have better performance at low temperatures.

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Bias Voltage DAC Operating at Cryogenic Temperatures for Solid-State Qubit Applications

Cited by 14 publications

References 7 publications

An 11-bit 0.008mm<sup>2</sup> charge-redistribution digital-to-analog converter operating at cryogenic temperature for large-scale qubit arrays

An 11-bit 0.008mm<sup>2</sup> charge-redistribution digital-to-analog converter operating at cryogenic temperature for large-scale qubit arrays

Single-electron pump in a quantum dot array for silicon quantum computers

A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers

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