Bias-temperature instability on the back gate of single-layer double-gated graphene field-effect transistors

Abstract

We study the positive and negative bias-temperature instabilities (PBTI and NBTI) on the back gate of single-layer double-gated graphene fieldeffect transistors (GFETs). By analyzing the resulting degradation at different stress times and oxide fields we show that there is a significant asymmetry between PBTI and NBTI with respect to their dependences on these parameters. Finally, we compare the results obtained on the high-k top gate and SiO 2 back gate of the same device and show that SiO 2 gate is more stable with respect to BTI.

Enhanced Intrinsic Voltage Gain in Artificially Stacked Bilayer CVD Graphene Field Effect Transistors

“…Since Al 2 O 3 is ALD deposited from a very thin (∼2 nm) Al seed layer, its interface quality & uniformity is better compared to e‐beam evaporated SiO 2 , which is more prone to having high defect densities. A detailed analysis on dielectric properties and their influence on device behavior is beyond the scope of this paper, but we refer to separate investigations on this matter …”

Effects of consecutive irradiation and bias temperature stress in p-channel power vertical double-diffused metal oxide semiconductor transistors

“…1) Because of that there is a great interest for intensive research and improving the device performances. 2) In many electronic devices, from metaloxide-semiconductor field effect transistors (MOSFET) to bipolar integrated circuits (ICs), the parts based on dielectrics are key components. Silicon dioxide (oxide) SiO 2 and oxidesemiconductor interface SiO 2 -Si are the most vulnerable parts of the MOS devices subjected to extreme, harsh environmental conditions or to the stress.…”