Bias Dependence of Total Ionizing Dose Effects on 28-nm Bulk MOSFETs

Zhang, Chunmin; Jazaeri, Farzan; Borghello, Giulio; Mattiazzo, Serena; Baschirotto, A.; Enz, Christian

doi:10.1109/nssmic.2018.8824379

Cited by 3 publications

(3 citation statements)

References 9 publications

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“…This is different from the historical worst-bias case-i.e., the switched-on bias condition V GB = V DD and V DS = 0 [23]. Nevertheless, these two bias conditions induce no big difference in the drain leakage current of our 28-nm bulk MOSFETs [24]. Moreover, in most analog circuits and particularly the analog FE electronics, MOSFETs are biased in saturation with a nonzero V DS except the switches working at a zero V DS .…”

Section: Methodsmentioning

confidence: 95%

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

Zhang

Jazaeri

Borghello

et al. 2019

IEEE Trans. Nucl. Sci.

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This paper characterizes and models the effects of total ionizing dose (TID) up to 1 Grad(SiO2) on the drain leakage current of nMOSFETs fabricated with a commercial 28-nm bulk CMOS process. Experimental comparisons among individual nMOSFETs of various sizes provide insight into the TID-induced lateral parasitic devices, which contribute the most to the significant increase up to four orders of magnitude in the drain leakage current. We introduce a semi-empirical physicsbased approach using only three parameters to model the parallel parasitic and total drain leakage current as a function of TID. Taking into account the gate independence of the drain leakage current at high TID levels, we model the lateral parasitic device as a gateless charge-controlled device by using the simplified charge-based EKV MOSFET model. This approach enables us to extract the equivalent density of trapped charges related to the shallow trench isolation oxides. The adopted simplified EKV MOSFET model indicates the weak inversion operation of the lateral parasitic devices.

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Section: Methodsmentioning

confidence: 95%

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

Zhang

Jazaeri

Borghello

et al. 2019

IEEE Trans. Nucl. Sci.

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“…The only difference in the implementation of the discriminator between the two prototypes is the switching circuit. In the current implementation the circuit has been changed to use p-type switches since they have proven to be more radiation resistant [25]. This change may have rise the discriminator pre-OC DC voltage point.…”

Section: Analog Front-end Characterizationmentioning

confidence: 99%

Timespot1: A 28nm CMOS Pixel Read-Out ASIC for 4D Tracking at High Rates

Cadeddu¹,

Frontini²,

Lai³

et al. 2022

Preprint

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A: We present the first characterization results of Timespot1, an ASIC designed in CMOS 28 nm technology, featuring a 32 × 32 pixel matrix with a pitch of 55 µm. Timespot1 is the first-born small-size prototype, conceived to read-out fine-pitch pixels with single-hit time resolution below 50 ps and input rates of several hundreds of kilohertz per pixel. Such experimental conditions will be typical of the next generation of high-luminosity collider experiments, from the LHC run5 and beyond. Each pixel of the ASIC has been endowed with a charge amplifier, a discriminator, and a Time-to-Digital Converter with time resolution around 30 ps and maximum read-out rates (per pixel) of 3 MHz. To respect system-level constraints, the timing performance have been obtained keeping the power budget per pixel below 40 µW. The ASIC has been tested and characterised in laboratory concerning its performance in terms of time resolution, power budget and sustainable rates. The ASIC will be hybridized on a matched 32 × 32 pixel sensor matrix and will be tested under laser beam and Minimum Ionizing Particles in the laboratory and at test beams. In this paper we present a description of the ASIC operation and the first results obtained from characterization tests concerning its performance in tracking measurements.

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“…For instance, Sun et al [9] investigated that GaN HEMTs which are with Schottky metallic gate structures typically exhibit a small shift after TID irradiation, while GaN HEMTs with MOS gates exhibit additional threshold voltage shift compared to similar devices with Schottky gates because of hole trapped in the gate oxide. Lidow et al [10] have studied the E-mode Schottky gate devices and concluded that the devices exhibited drifts of ∼0.2 V. Ives et al [11] have investigated the commercial radio frequency (RF) D-mode Schottky gate power HEMTs and indicated that the devices exhibited shifts of about 0.15 V. On the other hand, although significant progress has been made in understanding the underlying physics of TID irradiation in the Si MOSFETs [12][13][14][15][16][17][18][19], there is not much work undertaken on the TID effects in the Cascode GaN HEMTs. Chen et al [20] have investigated the high and low dose-rate radiation damage effects of the Cascode structure GaN power devices and found that the threshold voltage of the Cascode device was negatively drifted, having no enhanced low dose rate sensitivity effect.…”

Section: Introductionmentioning

confidence: 99%

Total-ionizing dose irradiation induced degradation behavior and mechanism of the Cascode GaN HEMTs

Cai

Chen

Zhou

2023

Semicond. Sci. Technol.

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In this article, the effects of total ionizing dose (TID) irradiation and the annealing treatment on the degradation of the commercial Cascode GaN high-electron-mobility transistors (HEMTs) were investigated, and low frequency noise method (LFN) was carried out to analyze the defects. The DC characteristics show that the device after TID irradiation with different doses exhibits a negative drift of threshold voltage (Vth) and a remarkable increase of drain-source current (Ids) with respect to the fresh one. Meanwhile, with increasing doses of the TID irradiation, the off-state drain leakage current increases, while the drain-source resistance decreases. The gate-lag characteristic gets better for the Cascode GaN HEMTs after TID irradiation. The transfer characteristics, output characteristics, blocking characteristics and capacitance characteristics of the devices can partly be restored by annealing treatment, but there is no pronounced influence on the gate-lag characteristics and drain-source resistance. The trap density extracted by the LFN method decreases in the Cascode GaN HEMTs after TID irradiation. The degradation behavior and mechanism of the Cascode GaN HEMTs under TID irradiation are analyzed. The experimental results may provide a useful reference for the design and space application of the Cascode GaN HEMTs.

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Bias Dependence of Total Ionizing Dose Effects on 28-nm Bulk MOSFETs

Cited by 3 publications

References 9 publications

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

Timespot1: A 28nm CMOS Pixel Read-Out ASIC for 4D Tracking at High Rates

Total-ionizing dose irradiation induced degradation behavior and mechanism of the Cascode GaN HEMTs

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