Behavioral Synthesis and Component Reuse with VHDL

Jerraya, Ahmed; Ding, Hong; Kission, P.; Rahmouni, Mohieddine

doi:10.1007/978-1-4615-6315-0

Cited by 39 publications

(16 citation statements)

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“…Proper partitioning allows abstracting the implementation details and maintain independence among the modules. Modularity enables the reuse of components (even previously synthesized, and synthesized with other tools) in the design [1], which could be specifically optimized, providing area savings and higher flexibility.…”

Section: Introductionmentioning

confidence: 99%

Inter-procedural resource sharing in High Level Synthesis through function proxies

Minutoli

Castellana

Tumeo

et al. 2015

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-Modular design is becoming increasingly important in High Level Synthesis (HLS) flows. Current HLS flows generate hierarchical and modular designs that mimic the structure and call graph of input specification translating functions into modules. Function calls are translated instantiating the callee module in the data-path of its caller, allowing for resource sharing when the same function is called multiple times. However, if two different callers invoke the same function, current HLS flows cannot share the instance of the module between the two callers, even if they invoke the function in a mutually exclusive way. In this paper, we propose a methodology that enables sharing of (sub)modules across modules boundaries. Sharing is obtained through function proxies, which act as forwarders of function calls in the original specification to shared modules without adding performance penalties. Building on the concept of function proxies, we propose a methodology and the related components to perform HLS of function calls through function pointers, without requiring complete static knowledge of the alias set (point-to set). We show that module sharing through function proxies provides valuable area savings without significant impacts on the execution delays, and that our synthesis approach for function pointers enables dynamic polymorphism.

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Section: Introductionmentioning

confidence: 99%

Inter-procedural resource sharing in High Level Synthesis through function proxies

Minutoli

Castellana

Tumeo

et al. 2015

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

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“…The rest of this section introduces the internal models used by AMICAL. For more details about this system see [JDKR96]. The bottom window shows the corresponding data path.…”

Section: Fig 1: Mixing Synthesis and Simulationmentioning

confidence: 99%

Architectural simulation in the context of behavioral synthesis

Jemai¹,

Kission²,

Jerraya³

Proceedings Design, Automation and Test in Europe

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“…Initially, the course introduces a VHDL design methodology for FPGA and ASIC, including synthesis, validation techniques and technology [7][8][9] (Figure 1a). In the second part, a class project, base on a real application, is presented.…”

Section: Design Flowmentioning

confidence: 99%