Baring it all to software: Raw machines

Waingold, E.; Taylor, Michael; Srikrishna, Devabhaktuni; Sarkar, Vivek; Lee, W.; Lee, V.; Kim, J.; Frank, Matthew I.; Finch, P. D.; Barua, Rajeev; Babb, Jonathan; Amarasinghe, Saman; Agarwal, Anant

doi:10.1109/2.612254

Cited by 467 publications

(245 citation statements)

References 11 publications

(2 reference statements)

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“…Also, we believe that StreamIt is a viable common machine language for grid-based architectures (e.g., [4,5,6]), just as C is a common machine language for von-Neumann machines. StreamIt abstracts away the target's granularity, memory layout, and network interconnect, while capturing the notion of independent processors that communicate in regular patterns.…”

Section: Discussionmentioning

confidence: 99%

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StreamIt: A Language for Streaming Applications

Thies

Karczmarek

Amarasinghe

2002

Lecture Notes in Computer Science

732

605

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Abstract. We characterize high-performance streaming applications as a new and distinct domain of programs that is becoming increasingly important. The StreamIt language provides novel high-level representations to improve programmer productivity and program robustness within the streaming domain. At the same time, the StreamIt compiler aims to improve the performance of streaming applications via stream-specific analyses and optimizations. In this paper, we motivate, describe and justify the language features of StreamIt, which include: a structured model of streams, a messaging system for control, a re-initialization mechanism, and a natural textual syntax.

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Section: Discussionmentioning

confidence: 99%

“…Secondly, general-purpose languages are a mismatch for the emerging class of grid-based architectures [4,5,6] that are especially well-suited for stream processing. Perhaps the primary appeal of C is that it provides a "common machine language" for von-Neumann architectures.…”

Section: Introductionmentioning

confidence: 99%

StreamIt: A Language for Streaming Applications

Thies

Karczmarek

Amarasinghe

2002

Lecture Notes in Computer Science

732

605

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“…Reconfigurable Architecture Workstation (raw) proposed by Agarwal and his colleagues at MIT [30,19,1] consists of processors that are sets of interconnected tiles each of which contains instruction and data memories, an arithmeticlogic unit, registers, configurable logic, and a programmable switch that supports both dynamic and static (compiler orchestrated) routing, interconnected by programmable interconnects. Compiling to a raw machine is complicated by two factors:…”

Section: Previous Workmentioning

confidence: 99%

Compiler Optimizations for Adaptive EPIC Processors

2001

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Abstract. Advances in VLSI technology have lead to a tremendous increase in the density and number of devices that can be manufactured in a single microchip. One of the interesting ways in which this silicon may be used is to leave portions of it uncommitted and re-programmable depending on an applications needs. In an earlier paper, we proposed a machine architecture for achieving this reconfigurability and compilation issues that such an architecture will face. In this paper, we will elaborate on the compiler optimization issues involved. In particular, we will outline a framework for code partitioning, instruction synthesis, configuration selection, resource allocation, and instruction scheduling. Partitioning is the problem of identifying code sections that may benefit by mapping them on to the programmable logic resources. The instruction synthesis phase generates suitable implementations for the candidates partitions and updates the machine description database with the new instructions. Configuration selection is the problem of narrowing down the choices of which synthesized instruction (from the set generated by the instruction synthesis phase) to use for each of the code regions that will be mapped to programmable logic. Unlike traditional optimizing compilers, the adaptive EPIC compiler must deal with the existence of synthesized instructions. Compilation techniques addressing each of these problems will be presented.

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“…Tiled architectures, such as TRIPS, WaveScalar and RAW [1][2] [3] exhibit very promising characteristics in that respect -namely, their decentralized organization eliminates several key scalability bottlenecks found in conventional superscalar processors, and reduces overall circuit complexity, effective wire delays and verification effort [4] [5]. These favorable characteristics make tiled architectures highly relevant to the future of high performance computing.…”

Section: Introductionmentioning

confidence: 99%

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

Farooq

John

Jacome

2009

High Performance Embedded Architectures and Compilers

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Abstract. Traditional predicated execution uses two techniques: top predication -in which only the head of the dependence chain is predicated, and bottom predication -in which only the tail of the dependence chain is predicated. Top predication prevents speculative execution, thus delivering minimum performance at minimum energy cost, while bottom predication allows full speculation of the dependence chain, resulting in maximum performance at maximum energy cost. In this paper, we propose a novel power-aware ILP extraction technique, denoted the 'elasticblock', that combines these two extremes, exposing superior energy vs. performance trade-offs. Each instruction in the elastic-block is explicitly guarded by two predicates: the speculative, and the final. Instruction's final predicate is generated using traditional if-conversion technique, while the speculative predicate has its default value statically assigned by the compiler, enabling it to make power-performance trade-offs in the code. Several energy saving code optimizations are proposed for the elasticblock structure.

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Baring it all to software: Raw machines

Abstract: This innovative approach eliminates the traditional instruction set interface and instead exposes the details of a simple replicated architecture directly to the compiler. This allows the compiler to customize the hardware to each application.

Cited by 467 publications

References 11 publications

StreamIt: A Language for Streaming Applications

StreamIt: A Language for Streaming Applications

Compiler Optimizations for Adaptive EPIC Processors

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

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