Automated synthesis of phase shifters for built-in self-test applications

Rajski, J.; Tamarapalli, Nagesh; Tyszer, Jerzy

doi:10.1109/43.875312

Cited by 74 publications

(52 citation statements)

References 12 publications

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“…For testing highly integrated circuits, the built-in self-test (BIST) [1], [2] technique is used as one of the design-fortestability (DFT) schemes to reduce test data volume. In BIST, test patterns are generated by a pseudorandom pattern generator (PRPG) such as a linear feedback shift register (LFSR) inside a chip and are provided to the scan chains in a circuit under test (CUT).…”

Section: Introductionmentioning

confidence: 99%

Modified PRPG for Test Data Reduction Using BAST Structure

Cai

Yotsuyanagi

Hashizume

2017

Journal of Signal Processing

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In order to reduce the volume of test data, built-in self test (BIST) and BIST-aided scan test (BAST) techniques have been proposed. To provide the test pattern generated by an automatic test pattern generator (ATPG) using BAST, we enhanced the structure of a pseudorandom pattern generator (PRPG) by inserting MUXes and NOT gates in the linear feedback shift register (LFSR) based on correlations of ATPG patterns. The procedures can achieve about 15 to 56% reduction in the volume of test data for BAST.

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Section: Introductionmentioning

confidence: 99%

Modified PRPG for Test Data Reduction Using BAST Structure

Cai

Yotsuyanagi

Hashizume

2017

Journal of Signal Processing

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“…1(a). The S-set of this cone is bound [7]. The general idea in these approaches is that the 0-7803-9390-2/06/$20.00 ©C2006 IEEE higher the bound, the lower the correlation and therefore the higher the expected fault coverage.…”

Section: Introductionmentioning

confidence: 99%

“…The rank of its residue matrix R2 is Set of this cone is S ={(1, 1), (1,4), (1,6), ( of maximally testable cones in the CUT is maximized. 7 This is a combinatorial optimization problem. We have (a) used an algorithm (referred as MaxLin for "maximizing linear independencies") that is based on simulated annealing to find Now let us assume that a phase shifter network is driving of T; Cone sets of CUT.…”

Section: Introductionmentioning

confidence: 99%

“…However, care should be taken while selecting channel -End If phase shifts as the hardware required to realize them could be large. Rajski et al [7] have proposed a method to find phase For each selected polynomial Qi(x) C Q-set, the H-set Hi shifters that require no more than a user-specified bound w of all possible channel phase shifts that satisfy the given tap on the number of taps (LFSR stages) that are needed to drive bound of w is generated. Further a group Ci of channel phase them.…”

Section: Introductionmentioning

confidence: 99%

“…Large phase present among the different test bit sequences of an LFSR, shifts are generally desirable as they result in less correlation have a negative impact on the fault coverage achieved as they and therefore higher fault coverage. In order to obtain large limit the number of unique patterns that are applied to the phase shifts, phase shifters (see, e.g., [7]) have been proposed CUT in violation of the principle ofpossible exhaustion [2]. in the literature.…”

Section: Introductionmentioning

confidence: 99%

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Phase Shifts and Linear Dependencies

Kakade

Kagaris

2006 IEEE International Symposium on Circuits and Systems

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Two-dimensional scan design is a widely used BIST a, |=°11111I1100100 architecture for pseudo-random and pseudo-exhaustive testing. 2 =°o 1 1 1 1 o 1 o 1 1 oo 1 o However, linear dependencies that arise due to the properties of the test-pattern generators in use have a negative impact a3 = o 1 000 I1 Io 1 o 1 1o on fault coverage. To alleviate this problem, networks of XOR a, gates known as phase shifters are often used. Existing techniques _F (b) for selecting phase shifts, such as those based on large channel S= = separations, lead to inadequate removal of linear dependencies. In Sca ch C this paper we present for the first time a method for the selection T of appropriate channel phase shifts to explicitly minimize linear dependencies. Experimental results corroborate the effect of the approach in increasing fault coverage.

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Crosstalk fault testing by the built‐in self‐test method with test points and phase shifters

Shimizu

Shirai

Itazaki

et al. 2004

Electron Comm Jpn Pt III

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SUMMARYWith the progressive decreases in size and increases in the speed of VLSI, guaranteeing signal integrity has become important. This paper focuses on crosstalk as a factor responsible for the violation of signal integrity and proposes a method of testing for crosstalk faults. The builtin self-test (BIST) method, which can detect crosstalk faults by using an M-sequence of a linear feedback shift register (LFSR), has been proposed. But since the output of the LFSR is used unaltered as a random test pattern, an insufficient number of crosstalk pulses is excited and some faults escape detection. We therefore propose the use of a new testing circuit which increases the number of crosstalk pulses that are excited and makes possible the detection of faults that were previously undetectable. The new testing circuit uses test points and phase shifter circuits which can output sequences that have arbitrary delays from the M-sequence. In addition, by changing the simulation method, it also becomes applicable to large-scale circuits for which such simulations could not be used in the past. We evaluate the detection rate and area overhead for several benchmark circuits and show that the method is effective in detecting crosstalk faults.

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Automated synthesis of phase shifters for built-in self-test applications

Cited by 74 publications

References 12 publications

Modified PRPG for Test Data Reduction Using BAST Structure

Modified PRPG for Test Data Reduction Using BAST Structure

Phase Shifts and Linear Dependencies

Crosstalk fault testing by the built‐in self‐test method with test points and phase shifters

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