Asymptotic Description of the Time and Temperature Hysteresis in the Framework of Landau-Khalatnikov Equation

Starkov, A. S.; Starkov, Ivan A.

doi:10.1080/00150193.2014.889544

Cited by 44 publications

(30 citation statements)

References 17 publications

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“…[33,[51][52][53][54][55] With the help of NC effect, the channel surface potential is amplified under a given V g , which contributes to the reduction in SS, thus acquiring a larger I on . The NC voltage (V NC ) is derived from the Landau-Khalatnikov (L-K) theory of ferroelectrics, [56,57] expressed as the following formula…”

Section: Discussionmentioning

confidence: 99%

Excellent Device Performance of Sub‐5‐nm Monolayer Tellurene Transistors

Yan

Pang

et al. 2019

Adv Elect Materials

105

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high carrier mobility, and good air stability, it has the possibility to serve as the channel material of postsilicon era. Disappointingly, most existing 2D semiconductors cannot meet these requirements simultaneously, including the most concerned 2D MoS 2 and black phosphorene (BP). [8][9][10][11][12] Experimentally, 2D MoS 2 FETs have been scaled down to the sub-10 nm region, [13][14][15] but the low on-current (<250 µA µm −1 ) mainly caused by the low carrier mobility fails to meet the International Technology Roadmap for Semiconductors (ITRS) requirements, [16] which is in accord with the results of the ab initio quantum transport simulations. [17] 2D BP FETs own high carrier mobility but are so sensitive to the air that their device performance degenerates when exposed under ambient condition. [18,19] Therefore, it is crucial to find a 2D channel material with a modest band gap, large drive current, and high air stability to continue Moore's law.Tellurium (Te), a p-type semiconductor, consists of individual helical Te chains that are stacked together by van der Waals force. [20] Recently, atomically thin tellurene (2D form of Tellurium) has been fabricated by a substrate-free solution process and molecular beam epitaxy on a graphene/6H-SiC substrate, respectively. [21][22][23] 2D tellurene possesses an anisotropic structure and is constituted of alternate tetragonal and hexagonal rings. [24,25] The band gap of tellurene monotonically decreasesThe merging 2D semiconductor tellurene (2D Group-VI tellurium) is a possible channel candidate for post-silicon field-effect transistor (FETs) due to its high carrier mobility, high drive current, and excellent air stability. The performance limits of sub-5-nm ML tellurene metal-oxide-semiconductor FETs (MOSFETs) are explored by employing exact ab initio quantum transport simulations. An optimized p-type ML tellurene MOSFET meets both the high performance (along both the armchair and the zigzag directions) and the low power (along the armchair direction) requirements of the International Technology Roadmap for Semiconductors (ITRS) at a gate length of 4 nm with a negative capacity dielectric. Hence, choosing ML tellurene as the channel material provides a novel route to continue the Moore's law to 4 nm.

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Section: Discussionmentioning

confidence: 99%

Excellent Device Performance of Sub‐5‐nm Monolayer Tellurene Transistors

Yan

Pang

et al. 2019

Adv Elect Materials

105

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“…The device can be considered as a series combination of a ferroelectric capacitor and a conventional MOSFET without imposing any boundary condition due to the presence of the intermediate layer. In this study, the device performance of an MFMIS structure is numerically calculated by combining Silvaco Atlas commercial simulator with the Landau-Khalatnikov (L-K) theory of ferroelectrics [17], [3].…”

Section: Simulation Methods and Device Structurementioning

confidence: 99%

Double-Gate Negative-Capacitance MOSFET With PZT Gate-Stack on Ultra Thin Body SOI: An Experimentally Calibrated Simulation Study of Device Performance

Saeidi

Jazaeri

Stolichnov

et al. 2016

IEEE Trans. Electron Devices

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In this work, we propose and investigate the high performance and low power design space of non-hysteretic negative capacitance MOSFETs for the 14 nm node based on the calibrated simulations using an experimental gate stack with PZT ferroelectric to obtain negative capacitance effect. All necessary parameters are extracted by carefully characterizing experimentally fabricated ferroelectric capacitors, to ensure realistic simulation results. The ferroelectric thickness obtained by the proposed approach leads to the maximum enhancement in the non-hysteretic operation of negative capacitance transistors. We report a clear and significant double improvement in (i) subthreshold swing and (ii) gate overdrive, using negative capacitance effect. Simulations using Silvaco TCAD coupled with a realistic Landau model of ferroelectrics demonstrates that a 14 nm node UTBB FDSOI-FET can operate at 0.26 V instead of 0.9 V gate voltage using negative capacitance effect, with an average subthreshold swing of 55 mV/decade at room temperature. The double gate structure is proposed to overcome the large mismatch between the ferroelectric and MOS capacitor to enhance the negative capacitance effect and reduce the ferroelectric's optimized thickness. A 14 nm node DG-NCFET can operate at 0.24 V gate voltage with an average subthreshold swing of 45 mV/decade.

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“…Table ). Also here, the calculations are based on an asymptotic solution of the Landau‐Khalatnikov equation . Figure compares the modeled P – E curves with available experimental data reported in Ref.…”

Section: Relaxor Modelmentioning

confidence: 91%

“…Quasi‐static P – E hystereses at 313 K in dependence on the direction of the external electric field are shown in Figure . These P – E hystereses were calculated using an asymptotic solution of the Landau‐Khalatnikov equation for periodic field oscillations that are much longer than the characteristic relaxation time of the relaxor ferroelectrics …”

Section: Relaxor Modelmentioning

confidence: 99%

Hysteresis Phenomena in Relaxor Ferroelectrics: Consideration of Polar Nanoregions

Starkov

Дедык

et al. 2017

Physica Status Solidi (b)

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Hysteresis phenomena of relaxor ferroelectrics have been modeled by considering spheroidal polar nanoregions covered by a thin shell of a linear dielectric both embedded into a ferroelectric matrix. The electric field within the spheroid is described by the Landau-Ginzburg-Devonshire equation. The resulting phase transition temperature is strongly dependent on the field direction. Calculations for single spheroids are generalized for an ensemble of random oriented spheroids. Finally, the temperature dependence of P-E hysteresis curve has been described with good accuracy for 0.7PbMg 1/3 Nb 2/3 O 3 -0.3PbTiO 3 as an exemplary relaxor ferroelectric.

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Asymptotic Description of the Time and Temperature Hysteresis in the Framework of Landau-Khalatnikov Equation

Cited by 44 publications

References 17 publications

Excellent Device Performance of Sub‐5‐nm Monolayer Tellurene Transistors

Excellent Device Performance of Sub‐5‐nm Monolayer Tellurene Transistors

Double-Gate Negative-Capacitance MOSFET With PZT Gate-Stack on Ultra Thin Body SOI: An Experimentally Calibrated Simulation Study of Device Performance

Hysteresis Phenomena in Relaxor Ferroelectrics: Consideration of Polar Nanoregions

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