Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques

Abstract

One of the severe issues of the downscaling of semiconductor devices is the threshold voltage reduction which significantly increases the leakage current. Thus, high threshold voltage (HVT) techniques are required to bring down the leakage hike for improved performances. In this paper, for the first time, we investigate the analog/RF and linearity performances of silicon (Si) FinFET by employing HVT techniques. Using well-calibrated TCAD models, to mitigate the leakage current, we analyzed the following approach to get HVT: 1) increasing channel doping (Nch′); 2) making drain-side underlap (Ldsu); 3) increasing gate length (Lg′). Two flavors of FinFETs viz Bulk and SOI (silicon-on-insulator) are suitably compared over their baseline counterpart, i.e., without HVTs. A thorough investigation of analog/RF metrics such as transconductance, output resistance, gate capacitance, cut-off frequency, gain-bandwidth, and transconductance-frequency product proves the eminence of Bulk-FinFET over its peer SOI-FinFET. In contrast, SOI-FinFET shows merits in intrinsic gain and linearity such as gm2, gm3, VIP2, VIP3, IIP3, IMD3, and 1-dB compression point. Thus, HVT techniques are worth analyzing for a FinFET architecture employed in analog/RF applications.

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

“…Using high Vth techniques (HVT) like enhanced channel doping, drain-side underlap and increased gate lengths in Si-FinFETs results in superior analog FoMs like transconductance, cut-off frequency, output resistance, gain-bandwidth product. SOI-FinFETs with HVT show merit in intrinsic gain and linearity parameters [30]. Several variations of the FinFET architecture, like use of high-K gate oxides, SOI structure, ferroelectric FinFETs and their circuit performance have been presented in detail in [31].…”

Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

“…Venkkataraman et al [14] derived the expression of threshold voltage considering the Si strain effect on the SiGe channel. Fei Ding et al [15] proposed a p-channel FinFET with a heterogeneous channel region (Si-Si 0.9 Ge 0.1 ) and compared it with a conventional p-channel FinFET. It was observed that the hetero-channel structure provides more ON current than the conventional one, and a low Ge mole fraction can enhance performance.…”

RF with linearity and non-linearity parameter analysis of gate all around negative capacitance junction less FET (GAA-NC-JLFET) for different ferroelectric thickness

“…From an application point of view, the extraction of linearity parameters of semiconductor devices must be taken into consideration as this has been one of the crucial parameters in order to reduce the intermodulation and receive high order harmonics as the output. On the other hand, sensitivity depends on device linearity, distortion and transconductance parameters [17,18]. The various non linearity parameters such as VIP2, VIP3, IMD3, g m2 & g m3 [19,20] for different ferroelectric thicknesses have been analyzed.…”