Area-time model for synthesis of non-pipelined designs

Jain, Rahul; Mlinar, Mitch; Parker, Alice C.

doi:10.1109/iccad.1988.122460

Cited by 30 publications

(13 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [6] a simple area-time estimation approach is presented which assigns a single delay and area value to each operation. The HAL system [7] also uses single propagation delay values for the scheduling to determine whether data operations can be chained.…”

Section: Introductionmentioning

confidence: 99%

Timing analysis in high-level synthesis

Kuehlmann

Bergamaschi

1992

IEEE/ACM International Conference on Computer-Aided Design

View full text Add to dashboard Cite

This paper presents a comprehensive timing model for behaviorablevel specifications and algorithms f o r timing analysis in high-level synthesis. It is based on a timing network which models the data flow as well as the control flow in the behavioral input specification. The delay values for the network modules are created by invoking the same logic synthesis procedure applied after behavioral synthesis. The timing network is built only once for a given behavioral description. Several parameters are used to ezplore different scheduling possibilities as well as different optimization modes (area, delay), without changing the network. The use of the timing model in conjunction with a path-based scheduling algorithm is presented. Results for several benchmarks attested the accuracy of this approach.

show abstract

Section: Introductionmentioning

confidence: 99%

Timing analysis in high-level synthesis

Kuehlmann

Bergamaschi

1992

IEEE/ACM International Conference on Computer-Aided Design

View full text Add to dashboard Cite

show abstract

“…For example, Figure 9 shows the distribution of delays as we vary the datapath bitwidth of an elliptical filter design. As the datapath 14.5 6 …”

Section: Experiments and Discussionmentioning

confidence: 99%

“…Datapath delay includes the delays of wiring, functional, interconnect, and storage units as described in Equation 10. Control unit delay includes the delays of control logic, next-state logic and state register as described in Equation 6. Wire/load delay takes into account the global wiring delay and the overall driven-load.…”

Section: Experiments and Discussionmentioning

confidence: 99%

Timing models for high-level synthesis

Chaiyakul¹,

Wu²,

Gajski³

Proceedings EURO-DAC '92: European Design Automation Conference

View full text Add to dashboard Cite

In this paper, we describe a timing model for clock estimation in high-level synthesis. In order to obtain realistic timing estimates, the proposed model considers datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous models. This model is well suited for automatic and interactive synthesis as well as feedback-driven synthesis where performance matrices can be rapidly and incrementally calculated.

show abstract

“…A model for Area-Time Estimation is presented in [7]. The dataflow graph is divided into a number of time steps.…”

Section: Previous Workmentioning

confidence: 99%

System clock estimation based on clock slack minimization

Narayan¹,

Gajski²

Proceedings EURO-DAC '92: European Design Automation Conference

View full text Add to dashboard Cite

When estimating a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operations into control steps. Prior to scheduling, most existing behavioral synthesis systems either require the designer to specify the clock cycle explicitly or require that the delays of the operators used in the design be Specified in multiples of a clock cycle. A bad choice of the clock cycle could adversely aflect the performance of the synthesized design. We present an algorithm for estimating the system clock based on a clock slack minimization criteria. The results obtained demonstrate that the clock cycle estimated by the Clock Slack Minimization method produces faster designs than previous solutions to the problem.

show abstract

Area-time model for synthesis of non-pipelined designs

Cited by 30 publications

References 3 publications

Timing analysis in high-level synthesis

Timing analysis in high-level synthesis

Timing models for high-level synthesis

System clock estimation based on clock slack minimization

Contact Info

Product

Resources

About