Architectures for multi-gigabit wire-linked clock and data recovery

Hsieh, Ming-ta; Sobelman, Gerald E.

doi:10.1109/mcas.2008.930152

Cited by 68 publications

(51 citation statements)

References 32 publications

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“…PLL-based CDR circuits have the advantage over alternative digital friendly CDRs that they have intrinsically a wide frequency capture range due to the ability to adapt both phase and frequency [19]. Additionally, they benefit from a wide bandwidth and have the ability to reject input jitter [20].…”

Section: Introductionmentioning

confidence: 99%

A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

Verbeke

Rombouts

Ramon

et al. 2018

IEEE J. Solid-State Circuits

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Abstract-Recently, there has been a strong drive to replace established analog circuits for multi-gigabit Clock and Data Recovery (CDR) by more digital solutions. We focused on PLLbased All-Digital CDR (AD-CDR) techniques which contain a Digital Loop Filter (DLF) and a Digital Controlled Oscillator (DCO) and pushed the digital integration up to a level where our DLF is entirely synthesized. To enable this, we found that extensive subsampling can be used to decrease the speed of the DLF while maintaining a good operation. Additionally, an Inverse Alexander phase detector and a 5.5-bit resolution DCO complete the AD-CDR architecture. As a result of the low-complexity and digital architecture, the AD-CDR occupies a compact active chip area of 0.050mm 2 and consumes only 46mW at 25Gb/s. This is the smallest area and lowest power consumption compared to the state-of-the-art. In addition, our implementation is highly tunable due to the synthesized logic and supports a wide operating range (12.5Gb/s-25Gb/s), which is a significantly larger range compared to previous work. Finally, thanks to our digital architecture the power dissipation decreases linearly while moving to the lower speeds of our operating range. This is in contrast with most prior work, making our design truly adaptive.

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Section: Introductionmentioning

confidence: 99%

A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

Verbeke

Rombouts

Ramon

et al. 2018

IEEE J. Solid-State Circuits

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“…There can be many ways of CDR depending on the clocking scheme of wireline data transmission system [7]. If a transmitter sends clock signal together with serial data to a receiver like in High-Definition Multimedia Interface (HDMI), the role of CDR circuit is relatively simple because it does not need to track the frequency offset between the transmitter and the receiver [8].…”

Section: Introductionmentioning

confidence: 99%

A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

Choi

Yoo

2014

IEICE Electron. Express

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A clock and data recovery (CDR) circuit for 1.5-5.0 Gb/s wireline transceiver is described. A phase locked loop (PLL) with dual phase frequency detector (PFD) and charge pump (CP) pairs performs the seamless phase rotation for the CDR circuit to track the phase and frequency difference. The CDR circuit implemented in a 65 nm CMOS process consumes 22.8 mW from a 1.2 V supply at 5.0 Gb/s. For 25 MHz jitter frequency, the CDR circuit can tolerate up to 0.21 unit-interval (UI) jitter with bit error rate (BER) smaller than 10 !12 .

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“…Fast locking capability of open-loop CDR circuits [3]- [8] makes them attractive solutions for these applications. However, open loop CDRs suffer from limited frequency tracking range and high jitter transfer [9]. Jitter transfer is not a serious issue for applications where no repeater is required [3], hence, open-loop CDRs are appropriate for such applications.…”

Section: Introductionmentioning

confidence: 99%