Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2013
DOI: 10.1145/2435264.2435303
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Abstract: Customized instructions (CIs) implemented using custom functional units (CFUs) have been proposed as a way of improving performance and energy efficiency of software while minimizing cost of designing and verifying accelerators from scratch. However, previous work allows CIs to only communicate with the processor through registers or with limited memory operations. In this work we propose an architecture that allows CIs to seamlessly execute memory operations without any special synchronization operations to g… Show more

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Cited by 4 publications
(3 citation statements)
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“…Vassiliadis et al [28] and Sun et al [29] proposed a hybrid approach to integrate a tightly-coupled and loosely-coupled accelerator. An approach for a tightly-coupled accelerator with direct memory access has been proposed in [30], [31], [32]. This approach suggests hardware architecture in which the accelerator can directly access a section of the CPU memory-mapped address space for reading or writing operations.…”
Section: A Graph-based Accelerator Extraction Methodsmentioning
confidence: 99%
“…Vassiliadis et al [28] and Sun et al [29] proposed a hybrid approach to integrate a tightly-coupled and loosely-coupled accelerator. An approach for a tightly-coupled accelerator with direct memory access has been proposed in [30], [31], [32]. This approach suggests hardware architecture in which the accelerator can directly access a section of the CPU memory-mapped address space for reading or writing operations.…”
Section: A Graph-based Accelerator Extraction Methodsmentioning
confidence: 99%
“…Kluter et al in [14] and [13] suggested modification to the cache controller to avoid using a rather costly hardware coherence protocol for solving the cache incoherence problem. In [15] the authors allow the accelerators to have direct access to the level one data-cache in the system and therefore able to initiate a memory transfer from the entire processor address space. All the write processes back to the memory only happens after the execution of the accelerator in order to ensure the validity of the data.…”
Section: A Custom Instructions With Memory Operationsmentioning
confidence: 99%
“…In [188] application that need to be considered during the selection of hardware accelerators with local memory blocks is also discussed.…”
Section: Related Workmentioning
confidence: 99%