Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array

Bouwens, Frank; Berekovic, Mladen; Sutter, Bjorn De; Gaydadjiev, Georgi

doi:10.1007/978-3-540-77560-7_6

Cited by 45 publications

(35 citation statements)

References 4 publications

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“…At cycle 0, PE[0,0] (row 0, column 0) and PE[0,2] are configured first to execute operations 0 and 1, respectively, and they send out the tokens to their consumers. At the next cycle, PE [1,0] and PE [1,2] receive the tokens from their producers and are configured to route the data to PE [1,1]. In a similar fashion, PEs are configured as tokens flow over the array and all the necessary PEs to execute the DFG are configured at cycle 4.…”

Section: Conceptsmentioning

confidence: 99%

“…The abundance of computation resources simply adds up the list for configurations to the control path. As a result, the total number of control bits to configure the whole array can reach nearly 1000 bits each cycle, and the control path takes up to 43% of the total power consumption in existing CGRA designs [3,2]. Moreover, control bits are read from the on-chip memory every cycle regardless of the array's utilization.…”

Section: Introductionmentioning

confidence: 99%

“…However, temporal mapping can be applied to only certain types of loops and it is not a general approach that can scale to different types of applications. [2] reduced the control path power of CGRAs as a by-product of an architecture exploration. A Pareto optimal design of a CGRA was discovered that required a lesser number of resources in the datapath thereby resulting in a power reduction in the control path.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A dataflow-centric approach to design low power control paths in CGRAs

Park

Mahlke

2009

2009 IEEE 7th Symposium on Application Specific Processors

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Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing high computation throughput, scalability, low cost, and energy efficiency, but suffer from relatively high control path power consumption. We take the concept of a token network from dataflow machines and apply it to the control path of CGRAs to increase efficiency. As a result, instruction memory power is reduced by 74% , the overall control path power by 56%, and the total system power by 25%.

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Section: Conceptsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A dataflow-centric approach to design low power control paths in CGRAs

Park

Mahlke

2009

2009 IEEE 7th Symposium on Application Specific Processors

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“…The characteristic of ALUs may be configured to one of kind phrase-stage operations of fixed-point numbers in line with the configuration words. The interconnection of PEs has several types, along with mesh, mesh plus [8], and morphosys topology [9]. The manner of configuration, CGRA can be divided into two categories: 1) full-reconfigurable CGRA and a couple of) partial-reconfigurable CGRA.…”

Section: Introductionmentioning

confidence: 99%

Implementation of FPGA based MRPMA for high performance applications

Phani¹,

Sujatha²,

Kishore³

et al. 2017

IJET

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In the last few decay, Network on Chip's (NoC) are the powerful chips for high speed communications pertaining to 802.11 Ethernet protocol which is a need to be reconfigurable for successful data frame transmission. The existing architectures like coarse grained reconfigurable, ALU cluster and expression grain reconfigurable architecture and look-up-table used in fine grained reconfigurable devices requires a lot of storage memory, hardware resources such as slices, cell area and cell delay. To tackle these issues, Multigrained Reconfiguration and Parallel Mapping Architecture (MRPMA) is proposed and their performance analysis parameters are calculated. The MRPMA uses the four contributions to optimize Processing Elements (PE's) operations: 1) Fast Fourier Transformation (FFT) to perform fixed point numbers to the configuration words, 2) Discrete Cosine Transformation (DCT) to analyze the data in the frequency domain, 3) Finite Impulse Response (FIR) for parallel mapping the data and 4) Channel encoder and decoder to encode the data and to calculate the shortest route from source to destination switch.

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“…Recently, as an alternative to the above special architectures like ASICs, Coarse-Grained Reconfigurable Architecture (CGRA) has grown in popularity as a way to provide a medium performance/power value and flexibility by reconfiguring the execution in a Functional Unit (FU) array. This is done mainly by re-constructing FU interconnections to represent individual data paths [2]- [4]. However, most current CGRAs still require a special compiler to instruct good reconfiguration.…”

Section: Introductionmentioning

confidence: 99%

A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction

Nakashima

Devisetti

et al. 2014

IEICE Trans. Inf. & Syst.

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SUMMARYGeneral purpose many-core architecture (MCA) such as GPGPU has recently been used widely to continue the performance scaling when the continuous increase in the working frequency has approached the manufacturing limitation. However, both the general purpose MCA and its building block general purpose processor (GPP) lack a tuning capability to boost energy efficiency for individual applications, especially computation intensive applications. As an alternative to the above MCA platforms, we propose in this paper our LAPP (Linear Array Pipeline) architecture, which takes a special-purpose reconfigurable structure for an optimal MIPS/W. However, we also keep the backward binary compatibility, which is not featured in most special hardware. More specifically, we used a general purpose VLIW processor, interpreting a commercial VLIW ISA, as the baseline frontend part to provide the backward binary compatibility. We also extended the functional unit (FU) stage into an FU array to form the reconfigurable backend for efficient execution of program hotspots to exploit parallelism. The hardware modules in this general purpose reconfigurable architecture have been locally zoned into several groups to apply preferable low-power techniques according to the module hardware features. Our results show that under a comparable performance, the tightly coupled general/special purpose hardware, which is based on a 180nm cell library, can achieve 10.8 times the MIPS/W of MCA architecture of the same technology features. When a 65 technology node is assumed, a similar 9.4x MIPS/W can be achieved by using the LAPP without changing program binaries.

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Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array

Cited by 45 publications

References 4 publications

A dataflow-centric approach to design low power control paths in CGRAs

A dataflow-centric approach to design low power control paths in CGRAs

Implementation of FPGA based MRPMA for high performance applications

A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction

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