Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array

Bouwens, Frank; Berekovic, Mladen; Kanstein, Andreas; Gaydadjiev, Georgi

doi:10.1007/978-3-540-71431-6_1

Cited by 84 publications

(46 citation statements)

References 3 publications

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“…These coarse grain blocks have dedicated routing channels. ADRES ( [18]) implemented and eval-uated several inter-connection topologies that includes simple mesh and more complex schemes, where one functional unit can transmit data to non-adjacent functional units in the same row or non-adjacent functional units in the same column. Pact XPP Technologies [21] propos architecture, which has a hierarchical array of coarse Processing Array Elements (PAEs) and a packet core is comprised of a rectangular array of ALU reconfigurable fabric architectures have sequential structure and use local registers or shared register files for storing data values.…”

Section: Background and Literature Reviewmentioning

confidence: 99%

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

Yadav

Stander

Jones

et al. 2013

VLSICS

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Coarse-grained reconfigurable fabrics (CGRF's) have great promise for achieving low-energy flexible designs for an application domain. However a universally accepted architecture for coarse-grained reconfigurable fabrics has not yet crystallized, and many architectural options are still un-der consideration by the research and industry community. One scientific question is how to efficiently route inputs through a CGRF. This paper addresses this question in part by exploring various alternative input solu-tions for a stripe-based fabric. Alternative architectural styles examined in this paper include (i) integrated constants (IC) approach where constants are loaded in the registers local to the functional units; (ii) inputs coming from the side (ICS) where both constants and variable inputs can be routed to the stripe directly where needed; (iii) ICS with extended vertical interconnect (ICS-EV); and (iv) a combination of dedicated pass gates (DPs) with standard, IC, ICS, and ICS-EV architecture styles.We implemented these architecture styles using 90 nm ASIC process from Synopsys. We perform a detailed area and energy analysis on these architectures and present quantitative results in this paper. We observed that the fabric with ICS and 50% DPs is the best among these options, providing 31% energy savings and 62% area savings over a baseline architecture for our benchmark set.

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Section: Background and Literature Reviewmentioning

confidence: 99%

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

Yadav

Stander

Jones

et al. 2013

VLSICS

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“…The transition from homogeneous to heterogeneous structures has been another recent development; notable implementations of heterogeneous CGRAs include RSPA [17] and ADRES [18]. Heterogeneity is another factor increasing differences in computation time, as slower and faster cells have to cohabit on the same array.…”

Section: A Architecturesmentioning

confidence: 99%

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

Ansaloni

Tanimura

Pozzi

et al. 2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Coarse-grained reconfigurable arrays (CGRAs) are a promising class of architectures conjugating flexibility and efficiency. Devising effective methodologies to map applications onto CGRAs is a challenging task, due to their parallel execution paradigm and constrained hardware resources. In order to handle complex applications, it is important to devise efficient strategies to partition a kernel into pieces that obey resource constraint and methodologies to schedule them on the underlying hardware. In this paper, we tackle these problems by proposing algorithms to address partitioning based on recursive searches over abstract trees. A novel scheduling strategy is also described that, leveraging differences in delays of various operations, is able to efficiently map operations on CGRA architectures. Experimental evidence on kernels derived from a diverse set of data flow graphs and EEMBC benchmarks demonstrate the efficacy of the described methods, which, when combined, achieve a higher runtime performance on a given mesh size than stateof-the-art approaches (as much as 38% for the benchmark applications considered).

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“…overview given in [1], the aspect of applying specially suited power reduction techniques on such architectures has not been covered in depth, so far. Often single figures and breakdowns of power consumption are given, like in [2] or [3], but no attempts were made to exploit architecture-specific features to reach a better power and energy efficiency, besides the configuration cache optimization given in [1]. In this work we combine the custom hierarchical and fine-grained automatic clock gating technique, see Section 3.2, and obtain a considerable increase in power efficiency for our case study CGRA.…”

Section: Related Workmentioning

confidence: 99%

“…Compare e.g. the data for the ADRES 4x4 design [3] accelerating a video processing application, with the relative total power and area contribution of the configuration memory of 37%. Regarding the fact that in CGRAs these components are active only a small percentage of the computation time, they are the ideal objects for modulelevel power reduction techniques, like for example clock and power gating.…”

Section: Component-level Power Minimizationmentioning

confidence: 99%

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures

Kissler

Strawetz

Hannig

et al. 2009

Journal of Low Power Electronics

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Abstract. Coarse-grained reconfigurable architectures deliver high performance and energy efficiency for computationally intensive applications like mobile multimedia and wireless communication. This paper deals with the aspect of power-efficient dynamic reconfiguration control techniques in such architectures. Proper clock domain partitioning with custom clock gating combined with automatic clock gating resulted in a 35% total power reduction. This is more than a threefold as compared to the single clock gating techniques applied separately. The corresponding case study application with 0.064 mW/MHz and 124 MOPS/mW power efficiency outperforms the major coarse-grained and general purpose embedded processor architectures by a factor of 1.7 to 28.

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Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array

Cited by 84 publications

References 3 publications

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures

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