Application of hardness-by-design methodology to radiation-tolerant ASIC technologies

Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits

“…However, these processes are typically two or three generations behind the commercial state-of-the-art. At the circuit level, there are a number of techniques that fall under the category of radiation-hardenedby-design (RHBD) (Alexander et al, 1996;Mavis and Alexander, 1997;Anelli et al, 1999;Lacoe et al, 2000). Special latches that are tolerant or immune to SEU have been developed using spatial redundancy because of the emphasis on sequential logic (Mavis and Eaton, 2002;Calin and Nicolaidis, 1996;Hazucha et al, 2003).…”

Development of a super B-factory monolithic active pixel detector—the Continuous Acquisition Pixel (CAP) prototypes

“…While the use of "enclosed" transistors [6,7] was not implemented in this design, previous measurements of the threshold voltage shift in this deep submicron process was determined to be quite acceptable. It should also be noted that results presented during this symposium on leakage currents for deeper sub-micron processes indicate that the benefits of this technique may not be significant for processes below 0.13µm feature size.…”

A Radiation Hard Bandgap Reference Circuit in a Standard 0.13 $\mu$m CMOS Technology

“…To eliminate the parasitic channels, the enclosed layout transistor (ELT) was introduced [5], [7]. In this geometry the gate completely surrounds the source of the transistor, avoiding any parasitic channels.…”

“…To clearly demonstrate the effectiveness of the radiation tolerant layout approach [5], [7], the same bandgap reference circuit was designed using the standard linear layout MOS transistors all over the design except for the DTMOST's structures. The DTMOST's were in the enclosed layout transistor geometry.…”

“…Recently, however, ASIC's fabricated in standard deep-submicron CMOS technologies have demonstrated robustness to SEL and TID, when special design topologies like enclosed (edgeless) transistor geometry and guard rings are used [4], [7], [8]. Without using a buried oxide, deep-submicron CMOS technologies have inherently a high tolerance to TID due to the reduced thickness of the gate oxide .…”