Analyzing the Impact of Radiation-Induced Failures in Programmable SoCs

Tambara, Lucas Antunes; Rech, Paolo; Chielle, Eduardo Ottobelli; Tonfat, Jorge; Kastensmidt, Fernanda Lima

doi:10.1109/tns.2016.2522508

Cited by 37 publications

(10 citation statements)

References 14 publications

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“…On the PS part, one module is responsible send to the controller the indexes while a second module reads the output of the SVM through an AXI interconnect and forwards it to a host PC through a serial port. The L2 cache of the ARM processor has been disabled to reduce the probability of faults affecting the PS [21]. No scrubbing mechanism nor the Xilinx Soft Error Mitigation (SEM) core IP were instantiated.…”

Section: Radiation Test Set-upmentioning

confidence: 99%

Effects of thermal neutron radiation on a hardware-implemented machine learning algorithm

Trindade

Benevenuti

Létiche

et al. 2021

Microelectronics Reliability

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Hardware-implemented machine learning algorithms are finding their way in various domains, including safety-critical applications. This has demanded these algorithms to perform correctly even in harsh environmental conditions, such as in avionics altitudes. Support Vector Machine (SVM) is an important Machine Learning that has been target of hardware implementation in recent years. This is the first work to asses both Binary and Multiclass SVMs under thermal neutron radiation, a type of particle noticeably present in high altitudes. A fault injection campaign along with a radiation test with the D50 thermal neutron source, at the Intitut Laue-Languevin, has been performed. The results show a high intrinsic fault tolerance for both varieties of the SVM algorithm, especially for the Multiclass SVM.

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Section: Radiation Test Set-upmentioning

confidence: 99%

Effects of thermal neutron radiation on a hardware-implemented machine learning algorithm

Trindade

Benevenuti

Létiche

et al. 2021

Microelectronics Reliability

View full text Add to dashboard Cite

show abstract

“…This scheme also protects internal core memories from bit-flips. Besides, all cache levels available for both ARM and MicroBlaze processor were disabled to improve device reliability, as it is proven that cache utilization adversely affects the radiation sensitivity of an embedded system [14].…”

Section: A Architecturementioning

confidence: 99%

Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors

Kasap

Wächter

Zhai

et al. 2020

2020 IEEE Nordic Circuits and Systems Conference (NorCAS)

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An attractive option for realizing applications in radiation environments is to employ All-Programmable Systemon-Chips (APSoCs) thanks to their high-performance computing and power efficiency merits. Despite APSoC's advantages, like any other electronic device, they are prone to radiation effects. Processors found in APSoCs must, therefore, be adequately hardened against ionizing-radiation to become a viable alternative for harsh environments. This paper proposes a novel triple-core lockstep (TCLS) approach to secure the Xilinx Zynq-7000 APSoC dual-core ARM Cortex-A9 processor against radiation-induced soft errors by coupling it with a MicroBlaze TMR subsystem in Zynq's programmable logic (PL) layer. The proposed strategy uses software-level checkpointing principles along with roll-back and roll-forward mechanisms (i.e. software redundancy), and hardware-level processor replication as well as checker circuits (i.e. hardware redundancy). Results of fault injection experiments show that the proposed solution achieved high soft error security by mitigating about 99% of bit-flips injected into both ARM cores' register data.

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“…Most of the traditional techniques for approximative computing today make use of neural networks implemented on FPGAs. Programmable logic tends to be more susceptible to radiation errors than hardcore processors [13]. Therefore, for safetycritical systems, software-based approximation running on hardcore processors is preferable over programmable logic implementations or softcore processors.…”

Section: The Proposed Fault Mitigation Approachmentioning

confidence: 99%

ARFT: An Approximative Redundant Technique for Fault Tolerance

Rodrigues¹,

Oliveira²,

Bosio³

et al. 2018

2018 Conference on Design of Circuits and Integrated Systems (DCIS)

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This paper presents a novel redundancy technique for software fault tolerance, named Approximative Redundant Fault Tolerance (ARFT). It uses approximate computing in order to provide the same error detection of a classic DWC method with less overhead. In this work ARFT was implemented to protect the ARM Cortex-A9 embedded into Zynq-7000 All Programmable SoC. An extensive fault injection campaign was performed to evaluate the proposed technique. Results show that distinct applications with different approximation methods present a big variation in terms of execution time, memory footprint and error detection capability. Performance analysis shows that ARFT can reduce the overhead in some benchmarks cases up to 40%.

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Analyzing the Impact of Radiation-Induced Failures in Programmable SoCs

Cited by 37 publications

References 14 publications

Effects of thermal neutron radiation on a hardware-implemented machine learning algorithm

Effects of thermal neutron radiation on a hardware-implemented machine learning algorithm

Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors

ARFT: An Approximative Redundant Technique for Fault Tolerance

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