Analyzing Reliability and Performance Trade-Offs of HLS-Based Designs in SRAM-Based FPGAs Under Soft Errors

Tambara, Lucas Antunes; Tonfat, Jorge; Santos, André Flores dos; Kastensmidt, Fernanda Lima; Medina, N. H.; Added, N.; Aguiar, Vitor A. P.; Aguirre, Fernando; Silveira, M. A. G.

doi:10.1109/tns.2017.2648978

Cited by 19 publications

(9 citation statements)

References 12 publications

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“…Thanks to the evolution of HLS tools, the precise modeling of the underlying hardware has been facilitated, which provides an opportunity to perform such studies comprehensively with an accuracy close to the real hardware. This approach is also followed by some recent works to study the resilience of several other applications [8], [9], [10], [11].…”

Section: A Different Methodologies To Study Nn Resiliencementioning

confidence: 99%

“…This approach can lead to a decreased development time with an early evaluation of the final design, while conforming to final power, energy, performance, and resilience goals in comparison to the in-silicon ASIC/FPGA implementation. For instance, an HLS-based approach has been used in recent research to study the resilience of accelerators [8], [9], [10], [11]. In this paper, we also use an HLS-based approach to study accelerator resilience.…”

Section: Introductionmentioning

confidence: 99%

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On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation

Salami

Ünsal

Kestelman

2018

2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

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Machine Learning (ML) is making a strong resurgence in tune with the massive generation of unstructured data which in turn requires massive computational resources. Due to the inherently compute-and power-intensive structure of Neural Networks (NNs), hardware accelerators emerge as a promising solution. However, with technology node scaling below 10nm, hardware accelerators become more susceptible to faults, which in turn can impact the NN accuracy. In this paper, we study the resilience aspects of Register-Transfer Level (RTL) model of NN accelerators, in particular fault characterization and mitigation. By following a High Level Synthesis (HLS) approach, first, we characterize the vulnerability of various components of RTL NN. We observed that the severity of faults depends on both i) application-level specifications, i.e., NN data (inputs, weights, or intermediate), NN layers, and NN activation functions, and ii) architectural-level specifications, i.e., data representation model and the parallelism degree of the underlying accelerator. Second, motivated by characterization results, we present a low-overhead fault mitigation technique that can efficiently correct bit flips, by 47.3% better than state-of-the-art methods.

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Section: A Different Methodologies To Study Nn Resiliencementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation

Salami

Ünsal

Kestelman

2018

2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

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“…The applicability and reliability of the HLS are discussed in [33][34][35][36][37]. Tambara et al [33] analyzed the utilization and performance of HLS-based optimization techniques, e.g., pipelining, loop unrolling, array partitioning, and function inlining. These techniques are used in three different combinations on matrix multiplication (MM), advanced encryption standard (AES), and adaptive differential pulse code modulation (ADPCM).…”

Section: Related Workmentioning

confidence: 99%

“…An IP is a package of HDL coding that can be used directly in system-level register transfer logic (RTL) design. Thus far, HLS-related research has mainly focused on the performance estimation of pre-built algorithms [33][34][35]. In [36,37], the authors presented application based works, but none are related to the image processing application.…”

Section: Related Workmentioning

confidence: 99%

HLS Based Approach to Develop an Implementable HDR Algorithm

Saha¹,

Banik²,

Kim³

2018

Electronics

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Hardware suitability of an algorithm can only be verified when the algorithm is actually implemented in the hardware. By hardware, we indicate system on chip (SoC) where both processor and field-programmable gate array (FPGA) are available. Our goal is to develop a simple algorithm that can be implemented on hardware where high-level synthesis (HLS) will reduce the tiresome work of manual hardware description language (HDL) optimization. We propose an algorithm to achieve high dynamic range (HDR) image from a single low dynamic range (LDR) image. We use highlight removal technique for this purpose. Our target is to develop parameter free simple algorithm that can be easily implemented on hardware. For this purpose, we use statistical information of the image. While software development is verified with state of the art, the HLS approach confirms that the proposed algorithm is implementable to hardware. The performance of the algorithm is measured using four no-reference metrics. According to the measurement of the structural similarity (SSIM) index metric and peak signal-to-noise ratio (PSNR), hardware simulated output is at least 98.87 percent and 39.90 dB similar to the software simulated output. Our approach is novel and effective in the development of hardware implementable HDR algorithm from a single LDR image using the HLS tool.

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“…In the case of the sequential implementation, weights are stored in Block-RAMS. We assume that such data, as well as configuration bits, may be protected by means of specific techniques such as memory scrubbing [26], complementarily to the fault tolerance of the neural model, thus avoiding an accumulation of faults after several clock cycles. Therefore, we take into account only bit-flip faults that can occur during each clock cycle in the weights of the currently handled neuron, or in the counter of neurons, or in reg d , or in reg BM U , or in registers that store the coordinates (position) of the BMU.…”

Section: Som Fault Tolerance Assessmentmentioning

confidence: 99%

Fault tolerance of self-organizing maps

Girau

Torres-Huitzil

2018

Neural Comput & Applic

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Bio-inspired computing principles are considered as a source of promising paradigms for fault-tolerant computation. Among bio-inspired approaches, neural networks are potentially capable of absorbing some degrees of vulnerability based on their natural properties. This calls for attention, since beyond energy, the growing number of defects in physical substrates is now a major constraint that affects the design of computing devices. However, studies have shown that most neural networks cannot be considered intrinsically fault tolerant without a proper design. In this paper, the fault tolerance of Self Organizing Maps (SOMs) is investigated, considering implementations targeted onto field programmable gate arrays (FPGAs), where the bit-flip fault model is employed to inject faults in registers. Quantization and distortion measures are used to evaluate performance on synthetic datasets under different fault ratios. Three passive techniques intended to enhance fault tolerance of SOMs during training/learning are also considered in the evaluation. We also evaluate the influence of technological choices on fault tolerance: sequential or parallel implementation, weight storage policies. Experimental results are analyzed through the evolution of neural prototypes during learning and fault injection. We show that SOMs benefit from an already desirable property: graceful degradation. Moreover, depending on some technological choices, SOMs may become very fault tolerant, and their fault tolerance even improves when weights are stored in an individualized way in the implementation.

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Analyzing Reliability and Performance Trade-Offs of HLS-Based Designs in SRAM-Based FPGAs Under Soft Errors

Cited by 19 publications

References 12 publications

On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation

On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation

HLS Based Approach to Develop an Implementable HDR Algorithm

Fault tolerance of self-organizing maps

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