DOI: 10.1109/date.2003.1253681
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Abstract: The increasing use of microprocessor cores in embedded systems, as well as mobile and portable devices, creates an opportunity for customizing the cache subsystem for improved performance. Traditionally, a design-simulate-analyze methodology is used to achieve desired cache performance. Here, to bootstrap the process, arbitrary cache parameters are selected, the cache subsystem is simulated using a cache simulator, based on performance results, cache parameters are tuned, and the process is repeated until an a…

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