Analysis of Transmission Characteristics of Copper/Carbon Nanotube Composite Through‐Silicon Via Interconnects

Fu, Kai; Zheng, Jian; Zhao, Wen‐Sheng; Hu, Yue; Wang, Gaofeng

doi:10.1049/cje.2019.06.005

Cited by 11 publications

(6 citation statements)

References 16 publications

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“…For Cu-CNT TSVs, the filling rate of CNTs is inversely proportional to the temperature increment and the maximum temperature [ 107 ]. Additionally, it exhibits less temperature sensitivity than Cu in both conductivity and high-frequency transmission performance [ 108 ].…”

Section: Through-silicon-via (Tsv)mentioning

confidence: 99%

Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects

Chen

Zhou

et al. 2022

Micromachines

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Along with deep scaling transistors and complex electronics information exchange networks, very-large-scale-integrated (VLSI) circuits require high performance and ultra-low power consumption. In order to meet the demand of data-abundant workloads and their energy efficiency, improving only the transistor performance would not be sufficient. Super high-speed microprocessors are useless if the capacity of the data lines is not increased accordingly. Meanwhile, traditional on-chip copper interconnects reach their physical limitation of resistivity and reliability and may no longer be able to keep pace with a processor’s data throughput. As one of the potential alternatives, carbon nanotubes (CNTs) have attracted important attention to become the future emerging on-chip interconnects with possible explorations of new development directions. In this paper, we focus on the electrical, thermal, and process compatibility issues of current on-chip interconnects. We review the advantages, recent developments, and dilemmas of CNT-based interconnects from the perspective of different interconnect lengths and through-silicon-via (TSV) applications.

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Section: Through-silicon-via (Tsv)mentioning

confidence: 99%

Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects

Chen

Zhou

et al. 2022

Micromachines

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“…where, ρ Cu is the resistivity of Cu material [3], [20]; W and T represent width and thickness of the interconnect line, respectively. The resistance model of a CNT interconnect line represents the equivalent p.u.l.…”

Section: Esc Model Of Hybrid Cu-cnt Interconnectmentioning

confidence: 99%

“…7. Next, the range of kinetic inductance and temperature are considered from 8-120 nH/μm and 300-500 K, respectively [17], [20]. The impact of these variations is analyzed on the inphase and outphase switching in coupled-two Cu-CNT interconnect lines, and the results are compared with the SWCNT lines network.…”

Section: Table 3 Cu-cnt Interconnects -Accuracy and Simulation Timementioning

confidence: 99%

“…The increased current density requirements for state-of-the-art technology nodes must be met by the on-chip interconnects somehow effectively and efficiently. Recent developments in copper-carbon nanotube (Cu-CNT) nanopackaging interconnects, present a credible solution while overcoming the discussed issues [12]- [20].…”

Section: Introductionmentioning

confidence: 99%

“…The performance modeling and reliability analysis of CNT interconnects have been done by various researchers [6], [8], [25]- [27]. However, the electrical modeling of Cu lines blended with CNT bundles is an interesting emerging research area of the nanopackaging domain [14], [18]- [20]. It has been observed that Cu-CNT interconnects provide two-order higher ampacity when compared to Cu [12].…”

Section: Introductionmentioning

confidence: 99%

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Transient Analysis of Hybrid Cu-CNT On-Chip Interconnects Using MRA Technique

Kumar

Kaushik

2022

IEEE Open J. Nanotechnol.

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This paper presents the transient analysis of the equivalent single conductor (ESC) model of hybrid Cu-CNT on-chip interconnects for nanopackaging using matrix rational approximation (MRA) modeling technique. The analysis of propagation delay and peak crosstalk noise is carried out for single and coupled Cu-CNT interconnect lines at 14 nm and 22 nm technology nodes. It has been observed that the proposed MRA model provides a speed-up factor of 131 compared to the HSPICE. An error of less than 1% confirms the accuracy of the proposed model compared to the SPICE simulations. It is observed that Cu-CNT lines are more immune to the crosstalk due to lesser coupling effects compared to Cu and CNT interconnects. The efficacy, accuracy, and comprehensive analysis using the proposed model ensures immense application possibility of the proposed model in the VLSI design automation tools at the nanopackaging level.

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