Analysis of interface state induced performance variation in LDD MOSFET's

Abstract

We have performed a two-dimensional analysis to study the interface trap effects on the drain current degradation in submicron MOSFET's. A hot electron stress induced interface trap generation model has been developed. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 ym LIID MOSFET was stressed at vds=7v and Vgs=3V for lo4 seconds. The drain current degradation was Characterized in both normal mode and reverse mode to compare the simulation. Our study shows that a significant drain current reduction appears in the linear region while the current reduction is only a few percentage points in the saturation region in normal mode. In reverse mode, the drain current degradation is significant in the entire region of operation.