Analysis of 6T SRAM Cell in Different Technologies

Abstract

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

Investigation of Radiation Hardened TFET SRAM Cell for Mitigation of Single Event Upset

“…The standby power of 6T TFET SRAM cell is measured by performing the transient analysis, and the procedure to compute power dissipation is explained in the Cadence manual [40]. During the power calculation in standby mode, WL is 0 then the two ATs (M5 and M6) are turned off and the content of the SRAM cell remains unchanged until the supply voltage exist [41].…”