2017
DOI: 10.1109/tpds.2017.2740285
View full text |Buy / Rent full text
|
Sign up to set email alerts
|

Abstract: Transactional Memory (TM) is a practical programming paradigm for developing concurrent applications. Performance is a critical factor for TM implementations, and various studies demonstrated that specialised transaction/thread scheduling support is essential for implementing performance-effective TM systems. After one decade of research, this article reviews the wide variety of scheduling techniques proposed for Software Transactional Memories. Based on peculiarities and differences of the adopted scheduling … Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
7
0
1

Year Published

2017
2017
2022
2022

Publication Types

Select...
2
2

Relationship

4
0

Authors

Journals

citations
Cited by 10 publications
(8 citation statements)
references
References 48 publications
(81 reference statements)
0
7
0
1
Order By: Relevance
“…Consequently, they do not represent suitable solutions to optimize the application performance under a power cap. On the opposite side, some tuning techniques for performance optimization of multithreaded workloads have been proposed for specific categories of applications and systems 11‐14 . However, they only target performance objectives, assuming that no power constraints exists.…”
Section: Literature Overviewmentioning
confidence: 99%
“…These solutions either try to sequentialize conflicting transactions on the same thread or control the concurrency degree of the STM-based application by changing the number of threads/transactions that are allowed to run in parallel. A comprehensive survey of the proposed techniques can be found [16]. Other techniques have been oriented to the optimization of the strategy for managing contention across concurrent transactions [17], [18].…”
Section: Related Workmentioning
confidence: 99%
“…They aim at (dynamically) determining the well-suited thread-level parallelism of TM-based applications. A recent survey of all these techniques can be found in [5].…”
Section: Related Workmentioning
confidence: 99%
“…In this section we report results assessing the effectiveness of our architecture 5 . We run experiments on a cluster of two 64-bit NUMA HP ProLiant servers, each equipped with four 2GHz AMD Opteron 6128 processors and 64 GB of RAM.…”
Section: Experimental Evaluationmentioning
confidence: 99%
“…In particular, the latter aspect requires the programmer's care to write transactional code that is idempotent in writing thread‐private data, thus increasing the complexity level. Concerning the performance issue, a great effort has been made by researchers to limit the performance impact of STM and to improve the STM performance through various approaches, spanning from alternative conflict detection and resolution algorithms, 4,8‐11 to dynamic concurrency control and dynamic tuning, 12,13 and to transaction scheduling techniques 14‐22 …”
Section: Introductionmentioning
confidence: 99%