MRS Proc. 2000 DOI: 10.1557/proc-610-b3.10 View full text
R. Annunziata, R. Bottini, P. Colpani, C. Cremonesi, G. Ghidini, E. Gomiero, G. Pavia, F. Pio, M. L. Polignano, G. Servalli, V. Higgs

Abstract: AbstractIn this paper we show that dopant decoration of process-induced defects is responsible for a failure mechanism of memory devices. From the electrical point-of-view, the defect-related failure consists in a source-to-drain resistive path formed by junction piping. This mechanism is made active by the very close spacing which is typical of present device structures. A device-like test structure is used for defect detection. This structure proves to be a very effective tool for studying the impact of vari…

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