An Parallel FPGA SAT Solver Based on Multi‐Thread and Pipeline

Li, Tiejun; Ma, Kefan; Zhang, Jianmin

doi:10.1049/cje.2021.08.001

Cited by 4 publications

(8 citation statements)

References 21 publications

(35 reference statements)

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“…Each try in line 1 of Algorithm 1 can assign different truth value compared to other tries, and they can be executed concurrently. This parallelization is similar to the 'multi-threaded execution' described in [14], [16]. We successfully placed T =4 try processing elements (PEs) within the FPGA resource constraint of the Alveo U250 platform (further details will be provided in Sections IV and V-B2).…”

Section: Try-level Parallelismmentioning

confidence: 98%

“…In each try (line , a new random truth value is assigned to every variable (line 2). Then it flips one variable at a time (lines [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. If the assignment satisfies the formula, the algorithm exits (line 5).…”

Section: ) Walksat Algorithm and Fpga Implementationmentioning

confidence: 99%

“…If not, a random unsatisfied clause is selected (line 7). The algorithm then computes the break score of the variables included in the chosen clause (lines [8][9][10][11][12][13][14][15][16][17]. A break score is the number of clauses that are currently true but become false when a variable's truth value is flipped.…”

Section: ) Walksat Algorithm and Fpga Implementationmentioning

confidence: 99%

“…The authors also extended their work to reduce the DRAM access latency with variable-way associate cache [15]. PprobSAT+ [16] employs multithreading and deep pipelining strategies to improve the throughput of the FPGA solver. The work in [17] utilizes multiple high-bandwidth memory channels to quickly fetch the clause data.…”

mentioning

confidence: 99%

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FYalSAT: High-Throughput Stochastic Local Search K-SAT Solver on FPGA

Choi,

Kim

2024

IEEE Access

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The satisfiability (SAT) problem is a fundamental challenge in computing and has a broad range of applications. This problem is NP-complete, and many algorithmic and architectural improvements have aimed at accelerating the SAT solver. But most existing stochastic local search (SLS) hardware solvers still rely on the outdated WalkSAT algorithm, and they have a reduced performance when handling problems with a large number of literals per clause. In this paper, we present FYalSAT, a field-programmable gate array (FPGA) based SLS SAT solver designed for high throughput. We incorporate a conflict-free data rearrangement scheme and a novel synchronization method to increase the parallelism. We also apply various optimizations such as clause prefetching, module overlapping, and pipelining to improve the performance. Experimental results demonstrate that FYalSAT outperforms the throughput of existing SLS FPGA solvers by 9.07×-110× for benchmarks with a large number of literals per clause.INDEX TERMS field-programmable gate arrays, satisfiability problem, stochastic local search, accelerator architecture I. INTRODUCTION

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Section: Try-level Parallelismmentioning

confidence: 98%

Section: ) Walksat Algorithm and Fpga Implementationmentioning

confidence: 99%

Section: ) Walksat Algorithm and Fpga Implementationmentioning

confidence: 99%

mentioning

confidence: 99%

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FYalSAT: High-Throughput Stochastic Local Search K-SAT Solver on FPGA

Choi,

Kim

2024

IEEE Access

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“…Both a pipeline structure and a parallel array exist in FPGA systematic structures. Therefore, whether an algorithm can be reconstructed in FPGA depends on mapping this algorithm into an FPGA systematic structure [24,25].…”

Section: Bpml Algorithms Built In Fpgamentioning

confidence: 99%

Fast γ Photon Imaging for Inner Surface Defects Detecting

Yao

Luo

Zhao

et al. 2021

Sensors

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Only a few effective methods can detect internal defects and monitor the internal state of complex structural parts. On the basis of the principle of PET (positron emission computed tomography), a new measurement method, using γ photon to detect defects of an inner surface, is proposed. This method has the characteristics of strong penetration, anti-corrosion and anti-interference. With the aim of improving detection accuracy and imaging speed, this study also proposes image reconstruction algorithms, combining the classic FBP (filtered back projection) with MLEM (maximum likelihood expectation Maximization) algorithm. The proposed scheme can reduce the number of iterations required, when imaging, to achieve the same image quality. According to the operational demands of FPGAs (field-programmable gate array), a BPML (back projection maximum likelihood) algorithm is adapted to the structural characteristics of an FPGA, which makes it feasible to test the proposed algorithms therein. Furthermore, edge detection and defect recognition are conducted after reconstructing the inner image. The effectiveness and superiority of the algorithm are verified, and the performance of the FPGA is evaluated by the experiments.

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Fasater: Fpga Based Sat Acceleration with Asynchronous Chain Circuits

Wang,

Yu,

et al. 2024

Preprint

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An Parallel FPGA SAT Solver Based on Multi‐Thread and Pipeline

Cited by 4 publications

References 21 publications

FYalSAT: High-Throughput Stochastic Local Search K-SAT Solver on FPGA

FYalSAT: High-Throughput Stochastic Local Search K-SAT Solver on FPGA

Fast γ Photon Imaging for Inner Surface Defects Detecting

Fasater: Fpga Based Sat Acceleration with Asynchronous Chain Circuits

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