An on-chip signal suppression countermeasure to power analysis attacks

Ratanpal, Girish B.; Williams, Ronald D.; Blalock, Travis N.

doi:10.1109/tdsc.2004.25

Cited by 91 publications

(45 citation statements)

References 13 publications

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“…The three most-used types of integrated DC-DC converter are: (i) the linear converter, a high-performance regulator with an external power current (I PS ) equal to the internal power current (I DD ) (no protection against power analysis attacks and an ideal power efficiency limited to V DD =V PS ), (ii) the shunt regulator presenting a good protection level because it permanently absorbs a constant current equal to the maximum current required by the load [4] and finally (iii) the switched capacitor converter (SCC) that has an ideal power efficiency of 100% and that absorbed a current uncorrelated to that provided to the load [5]. However, the area required by this latter usually exceeds the one available on a standard smart card chip.…”

Section: A Bi-channel Power Supply Topologymentioning

confidence: 99%

A bi-channel voltage regulator protecting smart cards against power analysis attacks

Telandro

Kussener

Barthélémy

et al. 2008

Analog Integr Circ Sig Process

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The bi-channel voltage regulator proposed in this paper has been specifically developed for smart cards. Its purpose is to protect the supplied system against power analysis attacks. It generates the internal power supply voltage from the external power supply voltage provided by card readers, while ensuring the uncorrelation between the external power supply current and the internal power supply current. The power supply current of an electronic system can be decomposed into a DC component, which contains little information, and an AC component, which handles considerably more. In order to reach a good compromise between regulation and security, while respecting the smart card stringent technological constraints, these two components are treated separately by a bi-channel power structure. The presented implementation has been simulated from the process parameters of a STMicroelectronics 0:18 lm CMOS technology. It provides a 1.8 V output voltage from a 2 to 5.5 V input voltage range. The structure has been sized to handle a 25 mA DC current while hiding a 20 MHz AC current presenting 75 mA peaks. Its estimated area is approximatively 0:8 mm 2 .

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Section: A Bi-channel Power Supply Topologymentioning

confidence: 99%

A bi-channel voltage regulator protecting smart cards against power analysis attacks

Telandro

Kussener

Barthélémy

et al. 2008

Analog Integr Circ Sig Process

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“…The techniques proposed using nondeterministic processors [17,21] have complex circuitry but do not have their overheads reported. The circuitry level solutions [30,33] cost significant area and energy overheads. The signal suppression technique [30] does not completely prevent DPA, but tries to make the attack more difficult.…”

Section: Related Workmentioning

confidence: 99%

“…The circuitry level solutions [30,33] cost significant area and energy overheads. The signal suppression technique [30] does not completely prevent DPA, but tries to make the attack more difficult. The current flattening technique, which is considered the most appropriate countermeasure for power analysis based SCAs, increases execution time by up to 75%, and flattens locally, based upon basic blocks.…”

Section: Related Workmentioning

confidence: 99%

A smart random code injection to mask power analysis based side channel attacks

Ambrose

Ragel

Parameswaran

2007

Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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One of the security issues in embedded system is the ability of an adversary to perform side channel attacks. Power analysis attacks are often very successful, where the power sequence dissipated by the system is observed and analyzed to predict secret keys.In this paper we show a processor architecture, which automatically detects the execution of the most common encryption algorithms, starts to scramble the power waveform by adding randomly placed instructions with random register accesses, and stops injecting instructions when it is safe to do so.Our technique prevents both Simple Power Analysis (SPA) and Differential Power Analysis (DPA). This approach has less overheads compared to previous solutions and avoids software instrumentation, allowing programmers with no special knowledge to use the system. Our processor model costs an additional area of 1.2%, and an average of 25% i n r unt i m e a nd 28. 5% i n energy ove r heads f or i ndust r y s t a ndard cryptographic algorithms.

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“…A malicious attacker hence can also subject the cryptographic chip to controlled radiations in a laboratory environment so as to make the integrated chip perform faulty. The advantage of this is that, the attacker is not permanently tampering or damaging the chip but only making it perform faulty in the presence of radiation event [9]. Thus one can leak out the required information such as IP, secret data and other side information without tampering the chip physically.…”

Section: Introductionmentioning

confidence: 99%

Multiple Bit Error Tolerant Galois Field Architectures Over GF (2m)

2012

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Radiation induced transient faults like single event upsets (SEU) and multiple event upsets (MEU) in memories are well researched. As a result of the technology scaling, it is observed that the logic blocks are also vulnerable to malfunctioning when they are deployed in radiation prone environment. However, the current literature is lacking efforts to mitigate such issues in the digital logic circuits when exposed to natural radiation prone environment or when they are subjected to malicious attacks by an eavesdropper using highly energized particles. This may lead to catastrophe in critical applications such as widely used cryptographic hardware. In this paper, novel dynamic error correction architectures, based on the BCH codes, is proposed for correcting multiple errors which makes the circuits robust against radiation induced faults irrespective of the location of the errors. As a benchmark test case, the finite field multiplier circuit is considered as the functional block which can be the target for major attacks. The proposed scheme has the capability to handle stuck-at faults that are also a major cause of failure affecting the overall yield of a nano-CMOS integrated chip. The experimental results show that the proposed dynamic error detection and correction architecture results in 50% reduction in critical path delay by dynamically bypassing the error correction logic when no error is present. The area overhead for the larger multiplier is within 150% which is 33% lower than the TMR and comparable to 130% overhead of single error correcting Hamming and LDPC based techniques.

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An on-chip signal suppression countermeasure to power analysis attacks

Cited by 91 publications

References 13 publications

A bi-channel voltage regulator protecting smart cards against power analysis attacks

A bi-channel voltage regulator protecting smart cards against power analysis attacks

A smart random code injection to mask power analysis based side channel attacks

Multiple Bit Error Tolerant Galois Field Architectures Over GF (2m)

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