J. Mikkelson, L. Hall, A. Malhotra, S. Seccombe, M. Wilson
THIS PAPER will describe a process developed to fabricate a 32b single chip CPU containing 450,000 transistors'. The major emphasis in process design was placed on geometry reduction by improved photolithography. Short channel devices and high density interconnect techniques were developed to use effectively the minimum geometrical features at each level.A high performance N-channel MOS process has been developed and implemented that uses efficiently 1.5pm line and l.Opm space minimum design rules t o fabrica…
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