An instruction-level functionally-based energy estimation model for 32-bits microprocessors

Brandolese, Carlo; Fornaciari, William; Salice, F.; Sciuto, D.

doi:10.1145/337292.337437

Cited by 53 publications

(35 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The main drawback of these techniques is that they rely on exhaustive simulation to find the energy consumption of each instruction and the interinstruction effects on the power consumption. The efficiency of the characterization can be improved by performing measurements on a limited subset of instructions and instruction sequences [7,8]. In [9,10], the same average energy is assumed for all instructions and the average power consumption while running an application program is calculated using the operating voltage of the processor and the clock frequency.…”

Section: Related Workmentioning

confidence: 99%

“…However, this requires calculating the power consumption of every gate for each instruction which is very time consuming. Most of existing energy estimation techniques including the techniques presented in [4][5][6][7][8][9][10][11][13][14][15][16][17][18][19][20][21] assume a linear approximation model for estimating the energy consumption of software running on a processor. However, none describes how to generate the linear approximation model for accurately characterizing the energy consumption of the processor.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Processor Energy Characterization for Compiler‐Assisted Software Energy Reduction

Gauthier

Ishihara

2012

Journal of Electrical and Computer Engineering

View full text Add to dashboard Cite

Energy consumption is a fundamental barrier in taking full advantage of today and future semiconductor manufacturing technologies. The paper presents our recent research activities and results on characterizing and reducing the energy consumption in embedded systems. Firstly, a technique for characterizing the energy consumption of embedded processors during an application execution is presented. The technique trains a per-processor linear approximation model for fitting it to the energy consumption of the processor obtained by postlayout simulation. Secondly, based on the energy model mentioned above, the paper shows techniques for reducing the energy consumption by optimally mapping program code, stack frames, and data items to the scratch-pad memory (SPM) of the processor memory space.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Processor Energy Characterization for Compiler‐Assisted Software Energy Reduction

Gauthier

Ishihara

2012

Journal of Electrical and Computer Engineering

View full text Add to dashboard Cite

show abstract

“…High-level microprocessor power modeling techniques range from analytical methods [4,15], based on e.g. statistical or information-theoretic techniques, to microarchitecture level instruction set simulators (ISSs) such as Wattch [6], Sim-Panalyzer [1] and SimplePower [25].…”

Section: Related Workmentioning

confidence: 99%

A High-level Microprocessor Power Modeling Technique Based on Event Signatures

Stralen

Pimentel

2008

J Sign Process Syst

View full text Add to dashboard Cite

This paper presents a technique for high-level power estimation of microprocessors. The technique, which is based on abstract execution profiles called 'event signatures', operates at a higher level of abstraction than commonly-used instruction-set simulator (ISS) based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. In this paper, we also compare our power estimation results to those from the instruction-level simulators Wattch and Sim-Panalyzer. In these experiments, we demonstrate that with a good underlying power model, the signature-based power modeling technique can yield accurate estimations (a mean error of 3.1% compared to Wattch in our experiments). At the same time, our signature-based power modeling technique is at least an order of magnitude faster than the simulations performed by Wattch or Sim-Panalyzer.

show abstract

“…Energy/power models with various accuracies have been proposed for processors [10,46,59], memory subsystems [21,30,51], buses [69] and operating systems [33]. The main method [32,58] is to quantify power consumption per instruction and inter-instruction effects.…”

Section: Future Directions: Compiler Per-formance and Power Cost Mod-mentioning

confidence: 99%

A component infrastructure for performance and power modeling of parallel scientific applications

Bui

Norris

Huck

et al. 2008

Proceedings of the 2008 compFrame/HPC-GECO Workshop on Component Based High Performance

View full text Add to dashboard Cite

Characterizing the performance of scientific applications is essential for effective code optimization, both by compilers and by high-level adaptive numerical algorithms. While maximizing power efficiency is becoming increasingly important in current high-performance architectures, there is little or no hardware or software support for detailed power measurements. Hardware counter-based power models are a promising method for guiding software-based techniques for reducing power. We present a component-based infrastructure for performance and power modeling of parallel scientific applications. The power model leverages on-chip performance hardware counters and is designed to model power consumption for modern multiprocessor/multicore systems. Our tool infrastructure includes application components as well as performance/power measurement and analysis components. We collect performance data using the TAU performance component and apply the power model in the performance and power analysis of a PETSc-based parallel fluid dynamics application by using the PerfExplorer component.

show abstract

An instruction-level functionally-based energy estimation model for 32-bits microprocessors

Cited by 53 publications

References 5 publications

Processor Energy Characterization for Compiler‐Assisted Software Energy Reduction

Processor Energy Characterization for Compiler‐Assisted Software Energy Reduction

A High-level Microprocessor Power Modeling Technique Based on Event Signatures

A component infrastructure for performance and power modeling of parallel scientific applications

Contact Info

Product

Resources

About