An FPGA Run-Time Parameterisable Log-Normal Random Number Generator

Echeverría, Pedro; Thomas, David B.; López‐Vallejo, Marisa; Luk, Wayne

doi:10.1007/978-3-540-78610-8_22

Cited by 4 publications

(7 citation statements)

References 11 publications

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“…This architecture was later improved [1], however the table-based method used there doesn't scale up to doubleprecision, as the size of the tables grows exponentially with the mantissa size.…”

Section: A Previous Workmentioning

confidence: 99%

“…In the present article, we propose yet another architecture for the floating-point evaluation of the exponential function, and its implementation in the open-source FloPoCo project 1 . Its main specificities are the following.…”

Section: B Contributionsmentioning

confidence: 99%

“…For instance, the single-precision version now involves just one 17x17-bit multiplier and 18Kbits of dual-port memory, and runs at 375MHz on a Virtex-4, which is a large improvement in all respects over the state of the art [1].…”

Section: B Contributionsmentioning

confidence: 99%

“…, and a mantissa must be 1.F ∈ [1,2). Thus the exponent and mantissa of the result may be obtained as…”

Section: Algorithm Overviewmentioning

confidence: 99%

“…On FPGAs, it has been used for scientific or financial Monte-Carlo simulations [1], for SPICE simulation [2], in phylogenetic tree reconstruction, in quantum chemistry simulations, and in the implementation of the power function [3] among others.…”

Section: Introductionmentioning

confidence: 99%

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A parameterized floating-point exponential function for FPGAs

Detrey

Dinechin

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

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Abstract-This article presents a generator of floating-point exponential operators targeting recent FPGAs with embedded memories and DSP blocks. A single-precision operator consumes just one DSP block, 18Kbits of dual-port memory, and 392 slices on Virtex-4. For larger precisions, a generic approach based on polynomial approximation is used and proves more resourceefficient than the literature. For instance a double-precision operator consumes 5 BlockRAM and 12 DSP48 blocks on Virtex-5, or 10 M9k and 22 18x18 multipliers on Stratix III. This approach is flexible and is demonstrated to scale up to quadrupleprecision, while enabling frequencies close to the FPGA's nominal frequency. All the proposed architectures are last-bit accurate for all the floating-point range. They are available in the open-source FloPoCo framework.

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Section: A Previous Workmentioning

confidence: 99%

Section: B Contributionsmentioning

confidence: 99%

Section: B Contributionsmentioning

confidence: 99%

“…, and a mantissa must be 1.F ∈ [1,2). Thus the exponent and mantissa of the result may be obtained as…”

Section: Algorithm Overviewmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A parameterized floating-point exponential function for FPGAs

Detrey

Dinechin

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

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Floating-Point Exponential

de Dinechin,

Kumm

2023

Application-Specific Arithmetic

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Floating-point exponential functions for DSP-enabled FPGAs

Dinechin

Pasca

2010

2010 International Conference on Field-Programmable Technology

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This article presents a floating-point exponential operator generator targeting recent FPGAs with embedded memories and DSP blocks. A single-precision operator consumes just one DSP block, 18Kbits of dual-port memory, and 392 slices on Virtex-4. For larger precisions, a generic approach based on polynomial approximation is used and proves more resource-efficient than the literature. For instance a doubleprecision operator consumes 5 BlockRAM and 12 DSP48 blocks on Virtex-5, or 10 M9k and 22 18x18 multipliers on Stratix III. This approach is flexible, scales well beyond double-precision, and enables frequencies close to the FPGA's nominal frequency. All the proposed architectures are last-bit accurate for all the floating-point range. They are available in the open-source FloPoCo framework.

show abstract

An FPGA Run-Time Parameterisable Log-Normal Random Number Generator

Cited by 4 publications

References 11 publications

A parameterized floating-point exponential function for FPGAs

A parameterized floating-point exponential function for FPGAs

Floating-Point Exponential

Floating-point exponential functions for DSP-enabled FPGAs

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