An FPGA implementation of whitted-style ray tracing accelerator

Park, Woo-Chan; Nah, Jae-Ho; Park, Jeong‐Soo; Lee, Kyung-Ho; Kim, Dong-Seok; Kim, Sang-Duk; Park, Jin‐Hong; Kim, Cheong-Ghil; Kang, Yoon-Sig; Yang, Seung Choul; Han, Tack-Don

doi:10.1109/rt.2008.4634650

Cited by 9 publications

(5 citation statements)

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“…We also integrated the proposed architecture into the ray tracing hardware of [5] and then implemented all on a Xilinx Virtex 5 LX330 chip with 84 MHz core speed. Our design occupies approximately 88% of the FPGA's logics cells and 78% of the FPGA's memory resources.…”

Section: Resultsmentioning

confidence: 99%

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The design of a texture mapping unit with effective MIP-map level selection for real-time ray tracing

Park¹,

Kim²,

Park

et al. 2011

IEICE Electron. Express

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Section: Resultsmentioning

confidence: 99%

“…This algorithm can provide MIP-map level selection using simple hardware logic. We also implement the proposed architecture by integrating it into the existing ray tracing hardware in [5]. Experimental results show our approach significantly reduces the computation requirements compared to [2].…”

Section: Introductionmentioning

confidence: 99%

The design of a texture mapping unit with effective MIP-map level selection for real-time ray tracing

Park¹,

Kim²,

Park

et al. 2011

IEICE Electron. Express

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“…A maior parte dos trabalhos encontrados realizava a implementação em uma linguagem de definição de hardware (HDL), em geral VHDL, e nestes trabalhos o Ray-Tracer era completamente implementado em hardware (desde a geração de raios até o cálculo de materiais e iluminação. Park et al [2008] desenvolveram um protótipo de acelerador para Ray-Tracer em FPGA com o objetivo de avaliar a eficiência de uma implementação ASIC. Nery et al [2010] implementaram um processador para Ray-Tracer em FPGA com um conjunto de instruções para o cálculo de pontos de interseção e a geração de raios em uma Unidade de Geração de Raios interna.…”

Section: Trabalhos Relacionadosunclassified

Proposta e Implementação de um Acelerador Eﬁciente em HLS para Ray Tracing

Sampaio¹,

Nery²,

Sena³

2020

Anais Do XXI Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2020)

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As arquiteturas reconﬁguráveis, como os chips FPGA, apresentam um alto potencial computacional a um baixo custo energético. Assim, o objetivo deste trabalho é propor e implementar um acelerador em síntese de alto nível (HLS) para execução eﬁciente do algoritmo de Ray-Tracing (i.e técnica de grande importância na área de renderização de imagens, especialmente por seus resultados ﬁsicamente precisos, apesar do seu alto custo computacional) nas FPGAs. Para isso várias estratégias de otimizações são propostas e avaliadas. Os resultados mostram que a versão mais rápida conseguiu alcançar resultados 2 vezes mais rápidos do que a versão para o processador ARM. Mais importante, os resultados obtidos ﬁcaram bem próximos de dois benchmarks de limite inferior propostos o que mostra a eﬁciência dos aceleradores.

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“…Park et al 11 created a Whitted‐style ray tracer accelerator prototype with the objective of creating a full ASIC design. In this prototype, Park describes that the scene is built outside of the hardware by a CPU and it sends the scene data to be rendered in the FPGA.…”

Section: Related Workmentioning

confidence: 99%

Enabling heterogeneous ray‐tracing acceleration in edge/cloud architectures

Sampaio

Sena

Nery

2020

Concurrency and Computation

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Summary The ray‐tracing algorithm is very costly regarding time complexity and while many techniques have been conceived over the years with the purpose of accelerating its execution, one stands out: parallelism exploitation of ray‐triangle intersection operations. In this sense, field‐programmable gate arrays (FPGAs) have plenty resources to run specialized accelerators that execute multiple operations in parallel. Moreover, modern FPGAs are embedded with multiprocessor systems‐on‐chip based on ARM architecture, which can be used simultaneously with the FPGA programmable logic to further accelerate the application execution. In this work, we present and analyze a reconfigurable accelerator for ray‐tracing specialized in computing ray‐triangle intersections at the network edge of a heterogeneous cloud computing environment. The accelerator is specified using Xilinx high‐level synthesis and is implemented in a Xilinx Zynq FPGA (XC7Z020‐1CLG400C). We also present an execution model which enables the exploitation of the available computing elements of the heterogeneous system: ARM Cortex‐A53, FPGA programmable logic, and cloud machines. Experimental performance and synthesis results show that the heterogeneous system can efficiently render a simplified version of the Stanford Bunny model when using the hardware accelerator with up to six instances of a ray‐triangle intersection unit together with the other computing resources.

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An FPGA implementation of whitted-style ray tracing accelerator

Cited by 9 publications

References 1 publication

The design of a texture mapping unit with effective MIP-map level selection for real-time ray tracing

The design of a texture mapping unit with effective MIP-map level selection for real-time ray tracing

Proposta e Implementação de um Acelerador Eﬁciente em HLS para Ray Tracing

Enabling heterogeneous ray‐tracing acceleration in edge/cloud architectures

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