An FPGA Implementation of Linear Kernel Support Vector Machines

Piña-Ramírez, Omar; Valdés-Cristerna, Raquel; Yáñez-Suárez, Oscar

doi:10.1109/reconf.2006.307784

Cited by 28 publications

(19 citation statements)

References 4 publications

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“…However, this increases the cycles needed to process a single vector. Hence, works that utilize such architectures have optimized it specifically for the vector dimensionality of the given problem and have been restricted to small scale data, with only a few hundred vectors and low dimensionality [9], [19], [20], and small-scale multiclass implementations [21] in order to be able to meet real-time constraints. In addition, these architectures cannot trade-off processing more SVs rather than vector elements, and hence, cannot efficiently deal with the different computational demands of the cascade SVM stages.…”

Section: Related Workmentioning

confidence: 99%

“…This has motivated a lot of research towards accelerating SVMs using parallel computing platforms such as Graphics Processing Units (GPUs) [7], and Field Programmable Gate Arrays (FPGAs) [8], [9], [10]. Implementations of SVMs on GPU platforms have been proposed recently, however, GPUs face challenges with regards to power consumption [11] and thus it is difficult to deploy them in embedded environments.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines

Kyrkou

Bouganis

Theocharides

et al. 2016

IEEE Trans. Neural Netw. Learning Syst.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines

Kyrkou

Bouganis

Theocharides

et al. 2016

IEEE Trans. Neural Netw. Learning Syst.

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show abstract

“…In [11], the authors presented FPGA implementation of the SVM classifier targeting a brain-computer interface, which requires real-time decisions. The design depends on doing the training offline using the LibSVM MATLAB extension based on linear kernels and the training coefficients along with the SVs are made available to the architecture.…”

Section: Relevant Workmentioning

confidence: 99%

“…However, for one of the cases, FPGA performed worse in terms of processing speed, consuming twice more time than the GPP. In addition, the FPGA architecture was nonscalable, limiting the implementation to six dimensions only [11].…”

Section: Relevant Workmentioning

confidence: 99%

Novel dynamic partial reconfiguration implementations of the support vector machine classifier on FPGA

Hussain

Benkrid

Şeker

2016

Turk J Elec Eng & Comp Sci

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Abstract:The support vector machine (SVM) is one of the highly powerful classifiers that have been shown to be capable of dealing with high-dimensional data. However, its complexity increases requirements of computational power. Recent technologies including the postgenome data of high-dimensional nature add further complexity to the construction of SVM classifiers. In order to overcome this problem, hardware implementations of the SVM classifier have been proposed to benefit from parallelism to accelerate the SVM. On the other hand, those implementations offer limited flexibility in terms of changing parameters and require the reconfiguration of the whole device. The latter interrupts the operation of other tasks placed on the hardware device. In this work, two flexible hardware implementations of the SVM classifier are proposed, namely A1 and A2 classifiers with successful applications in a microarray dataset. In addition, two dynamically and partially reconfigurable (DPR) architectures of the SVM classifier are presented. The A1 and A2 architectures have achieved up to 61 × and 49 × speed-up, respectively, over the equivalent general purpose processor. Furthermore, the DPR implementations achieved at least ∼ 8 × reduction in reconfiguration time compared to non-DPR implementation. This is a significant achievement that can be easily adapted in other application domains of a similar nature.

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“…A few surveys of neural network hardware have been published in [30]- [34] where several hundred works were listed. Support vector machine (SVM) hardware also seems attractive [35]- [41]. As Heemskerk [30] indicates, the hardware implementation of neural networks is expensive in terms of development time and hardware resources.…”

Section: Introductionmentioning

confidence: 99%

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching

Koide

Mattausch

2012

IEICE Trans. Inf. & Syst.

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SUMMARYIn this paper, we propose a hardware solution for overcoming the problem of high computational demands in a nearest neighbor (NN) based multi-prototype learning system. The multiple prototypes are obtained by a high-speed K-means clustering algorithm utilizing a concept of software-hardware cooperation that takes advantage of the flexibility of the software and the efficiency of the hardware. The one nearest neighbor (1-NN) classifier is used to recognize an object by searching for the nearest Euclidean distance among the prototypes. The major deficiency in conventional implementations for both K-means and 1-NN is the high computational demand of the nearest neighbor searching. This deficiency is resolved by an FPGA-implemented coprocessor that is a VLSI circuit for searching the nearest Euclidean distance. The coprocessor requires 12.9% logic elements and 58% block memory bits of an Altera Stratix III E110 FPGA device. The hardware communicates with the software by a PCI Express (×4) local-bus-compatible interface. We benchmark our learning system against the popular case of handwritten digit recognition in which abundant previous works for comparison are available. In the case of the MNIST database, we could attain the most efficient accuracy rate of 97.91% with 930 prototypes, the learning speed of 1.3 × 10 −4 s/sample and the classification speed of 3.94 × 10 −8 s/character.

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An FPGA Implementation of Linear Kernel Support Vector Machines

Cited by 28 publications

References 4 publications

Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines

Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines

Novel dynamic partial reconfiguration implementations of the support vector machine classifier on FPGA

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching

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