An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique

A Supply Pushing Reduction Technique for <italic>LC</italic> Oscillators Based on Ripple Replication and Cancellation

“…In [24], a correlation-based calibration scheme is implemented, but non-ideal effects, such as an offset of the mixer lead to incorrect calibration results. Moreover, compared with other state-of-the-art LDOs with on-chip capacitors [6], [7], [24], [42], our work demonstrates one of the highest PSR at 10 MHz with less or comparable (extra) power. The total on-chip capacitance used in the proposed design is also the lowest, thus occupying the smallest area.…”

Capacitor‐less FVF low drop‐out regulator with active feed‐forward compensation and efficient slew‐rate enhancer circuit

“…This LDO achieves lesser settling time of 250 ns during overshoot and 80 ns during undershoot with lesser quiescent current of as compared with reported works. Moreover, the gate dominant pole compensation with MC and AFFC in this work eliminates the minimum load current demand unlike in other gate dominant LDOs reported in [10, 11]. The better transient response of LDO with the low quiescent current is visible in Fig.…”

“…The improved FVF LDO is compared with the output capacitor‐less LDOs reported in [2, 4, 10, 11, 22, 23] and given in Table 2. This LDO achieves lesser settling time of 250 ns during overshoot and 80 ns during undershoot with lesser quiescent current of as compared with reported works.…”

Analysis and Design of Power Supply Circuits for RF Oscillators

“…At frequencies below the dominant pole (i.e., f D ≈ 10 MHz), the PSR is ∼ −40 dB, as predicted by Eq. (22). In the simulation, the efficiency degradation due to I res , I Q , and V O D is 0.92, 0.87 and 0.89, respectively, leading to a total power efficiency of 71%.…”

“…where r O,E A is the output impedance of the error amplifier, R OU T = R L ||(R F 1 + R F 2 )||r DS P , r DS P is the output impedance of M P , C gd P and C gs P is the gate-to-drain and gate-to-source capacitance of M P , respectively. Based on the location of the dominant pole (ω D ), the LDO topologies can be divided into two categories [22] whose PSR profile is sketched in Fig. 1 (b).…”