An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current

Lim, Younghyun; Lee, Jeonghyun; Lee, Yongsun; Song, Seong-Sik; Kim, Hong-Teuk; Lee, Ockgoo; Choi, Jae Hyun

doi:10.1109/tvlsi.2017.2742603

Cited by 21 publications

(12 citation statements)

References 27 publications

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“…In [24], a correlation-based calibration scheme is implemented, but non-ideal effects, such as an offset of the mixer lead to incorrect calibration results. Moreover, compared with other state-of-the-art LDOs with on-chip capacitors [6], [7], [24], [42], our work demonstrates one of the highest PSR at 10 MHz with less or comparable (extra) power. The total on-chip capacitance used in the proposed design is also the lowest, thus occupying the smallest area.…”

Section: Measurement Resultsmentioning

confidence: 81%

“…10(c) show that the PN degradation is only 1.16 dBc at 100-kHz frequency offset. Note that the reported spot noise (as expressed in nV/ √ Hz unit) of the LDOs in [6] and [7] at 100 kHz is more than 30× the value shown in Fig. 10(a).…”

Section: Oscillator Implementationmentioning

confidence: 72%

“…This appears to be in conflict with the current trend of full system integration, which favors switched-capacitor (SC)-based dc-dc converters clocked at much higher frequencies than with the traditional inductor-based converters. The higher switching frequencies now benefit the dc-dc converters but require large LDO currents and/or complex circuit techniques [6], [7].…”

mentioning

confidence: 99%

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A Supply Pushing Reduction Technique for <italic>LC</italic> Oscillators Based on Ripple Replication and Cancellation

Chen

Liu

Zong

et al. 2019

IEEE J. Solid-State Circuits

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Section: Measurement Resultsmentioning

confidence: 81%

Section: Oscillator Implementationmentioning

confidence: 72%

mentioning

confidence: 99%

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A Supply Pushing Reduction Technique for <italic>LC</italic> Oscillators Based on Ripple Replication and Cancellation

Chen

Liu

Zong

et al. 2019

IEEE J. Solid-State Circuits

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“…Note that oscillators with better phase noise (i.e., higher Q or P DC ) impose even more stringent noise requirements on their supply voltage. 1 Note that the reported spot noise of LDOs with high current efficiency (i.e., > 90%) is much higher than the supply noise tolerated by the oscillator [11], [12], [28], [29]. To reduce the output noise of the LDO, its quiescent current should be increased, which leads to a severe current efficiency degradation (e.g., 70% in [30]) or an external filtering capacitor must be used [8].…”

Section: A Supply Noise Requirementsmentioning

confidence: 99%

“…Since the LDOs are noisy, bulky and inefficient [8], [10]- [12], it would appear beneficial for the IoT circuitry to be connected directly to the buck converter. However, the LDO elimination would impose several challenges on the design of the DC-DC converter and the LC oscillator.…”

mentioning

confidence: 99%

A Switched-Capacitor DC-DC Converter Powering an LC Oscillator to Achieve 85% System Peak Power Efficiency and −65dBc Spurious Tones

Urso

Chen

Staszewski

et al. 2020

IEEE Trans. Circuits Syst. I

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In this paper, we propose a new scheme to directly power a 4.9-5.6 GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3-2.2 V and <2 mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is <1.5 nV/ √ Hz, which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to < −65 dBc under the 30 mV pp ripple of the converter.

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High PSR external capacitor‐less LDO with adaptive supply‐ripple cancellation technique

Xu,

Xie,

Chen

et al. 2024

Circuit Theory & Apps

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This work presents an external capacitor‐less low‐dropout regulator (CL‐LDO) with high power supply rejection (PSR) over a wide frequency and load current ( ) range. The high PSR is implemented with an adaptive supply‐ripple cancellation (ASRC) technique. The proposed ASRC circuit consists of a buffer with diode‐connected structure and an adjusting unit. The novel buffer introduces the supply ripple through the diode‐connected transistor to the gate of the pass transistor, enhancing the PSR in the range of 1 MHz. Additionally, the adjusting unit trims the current of the buffer continuously according to the magnitude of to optimize the PSR adaptively. Designed in a 55 nm CMOS process with an input voltage of 1.4 V, the proposed LDO achieves −69 dB and −55 dB PSR at 100 KHz and 1 MHz for 50 mA of , respectively. Moreover, the maximum current efficiency of the LDO is 99.8% at a full of 50 mA.

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An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current

Cited by 21 publications

References 27 publications

A Supply Pushing Reduction Technique for <italic>LC</italic> Oscillators Based on Ripple Replication and Cancellation

A Supply Pushing Reduction Technique for <italic>LC</italic> Oscillators Based on Ripple Replication and Cancellation

A Switched-Capacitor DC-DC Converter Powering an LC Oscillator to Achieve 85% System Peak Power Efficiency and −65dBc Spurious Tones

High PSR external capacitor‐less LDO with adaptive supply‐ripple cancellation technique

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