An enhanced perturbing algorithm for floorplan design using the O-tree representation

Pang, Yingxin; Cheng, Chung‐Kuan; Yoshimura, Takeshi

doi:10.1145/332357.332395

Cited by 58 publications

(32 citation statements)

References 5 publications

(6 reference statements)

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“…Importantly, those algorithms do not change the semantics of evaluation -they only improve runtime, and lead to better solution quality by enabling a larger number of iterations during the same period of time. While O-trees [Pang et al 2000] and corner block lists [Hong et al 2000] can be evaluated in linear time, the difference in complexity is dwarfed by implementation variations and tuning, e.g., the annealing schedule. The implementation reported by Tang et al [Tang and Wong 2001] seems to outperform most known implementations, suggesting that the sequence-pair is a competitive floorplan representation.…”

Section: Fixed-outline Floorplanningmentioning

confidence: 99%

Combinatorial techniques for mixed-size placement

Adya

Markov

2005

ACM Trans. Des. Autom. Electron. Syst.

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While recent literature on circuit layout addresses large-scale standard-cell placement, the authors typically assume that all macros are fixed. Floorplanning techniques are very good at handling macros, but do not scale to hundreds of thousands of placeable objects. Therefore we combine floorplanning techniques with placement techniques to solve the more general placement problem. Our work shows how to place macros consistently with large numbers of small standard cells. Proposed techniques can also be used to guide circuit designers who prefer to place macros by hand.We address the computational difficulty of layout problems involving large macros and numerous small logic cells at the same time. Proposed algorithms are evaluated in the context of wirelength minimization because a computational method that is not scalable in optimizing wirelength is unlikely to be successful for more complex objectives (congestion, delay, power, etc.) We propose several different design flows to place mixed-size placement instances. The first flow relies on an arbitrary black-box standard-cell placer to obtain an initial placement and then removes possible overlaps using a fixed-outline floorplanner. This results in valid placements for macros, which are considered fixed. Remaining standard cells are then placed by another call to the standard-cell placer. In the second flow a standard-cell placer generates an initial placement and a force-directed placer is used in the ECO mode to generate an overlap-free placement. Empirical evaluations on ibm benchmarks show that in most cases our proposed flows compare favorably with previously published mixed-size placers Kraftwerk, mixed-size floor-placer proposed at DATE 2003 and are competitive with mPG-MS.

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Section: Fixed-outline Floorplanningmentioning

confidence: 99%

Combinatorial techniques for mixed-size placement

Adya

Markov

2005

ACM Trans. Des. Autom. Electron. Syst.

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“…As shown in TABLE III, TCG achieves average improvements of 2.22%, 1.18%, 2.04%, and 3.54% in area utilization compared to O-tree, B*-tree, enhanced O-tree, and CBL, respectively. The runtimes are significantly smaller than O-tree and B*-tree, and comparable to the enhanced O-tree [13]. Fig 7 (left) shows the resulting placement for ami49 with area optimization.…”

Section: Resultsmentioning

confidence: 86%

“…The TCG package is available at http://cc.ee.ntu.edu.tw/ ywchang/research.html. We compared TCG with O-tree [2], B*-tree [1], enhanced O-tree [13], and CBL [3] based on the five MCNC benchmark circuits listed in TABLE II. Columns 2, 3, 4, and 5 of TABLE II list the respective numbers of modules, I/O pads, nets, and pins of the five circuits.…”

Section: Resultsmentioning

confidence: 99%

“…The area of a placement is measured by that of the minimum bounding box enclosing the placement. The area and runtime comparisons among O-tree [2], B*-tree [1], enhanced O-tree [13], CBL [3], and TCG are listed in TABLE III. As shown in TABLE III, TCG achieves average improvements of 2.22%, 1.18%, 2.04%, and 3.54% in area utilization compared to O-tree, B*-tree, enhanced O-tree, and CBL, respectively.…”

Section: Resultsmentioning

confidence: 99%

“…There exist a few floorplan representations in the literature, e.g., [1], [2], [3], [7], [8], [9], [10], [11], [12], [13], [17], [18]. We shall first review these representations and the types of floorplans that they can represent.…”

Section: A Previous Workmentioning

confidence: 99%

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TCG: a transitive closure graph-based representation for non-slicing floorplans

Lin¹,

Chang²

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)

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Abstract-In this paper, we introduce the concept of the P*-admissible representation and propose a P*-admissible, transitive closure graph-based representation for general floorplans, called TCG, and show its superior properties. TCG combines the advantages of popular representations such as sequence pair, BSG, and B*-tree. Like sequence pair and BSG, but unlike O-tree, B*-tree, and CBL, TCG is P*-admissible. Like B*-tree, but unlike sequence pair, BSG, O-tree, and CBL, TCG does not need to construct additional constraint graphs for the cost evaluation during packing, implying faster runtime. Further, TCG supports incremental update during operations and keeps the information of boundary modules as well as the shapes and the relative positions of modules in the representation. More importantly, the geometric relation among modules is transparent not only to the TCG representation but also to its operations, facilitating the convergence to a desired solution. All these properties make TCG an effective and flexible representation for handling the general floorplan/placement design problems with various constraints. Experimental results show the promise of TCG.

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Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

Hoo

Kanesan

Ramiah

2013

Circuit Theory & Apps

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From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time-to-market of the product. A new perturbation method, called Cull-and-Aggregate Bottom-up Floorplanner (CABF), which consists of culling and aggregating stages, is developed to perform variable-order automated floorplanning for VLSI. CABF will generate VLSI floorplan layout by calculating the modules' dimensions' differences (hard module floorplanning problems) and the modules' areas' differences (soft module floorplanning problems). Through mathematical derivation, the hard modules floorplanning area minimization cost function (two-dimensional) during culling stage is proven that a dimensional reduction can be carried out to be the difference-based cost function (one-dimensional) which simplifies the computation. During the culling stage, CABF employs linear ordering method to select and determine the order of modules where this linear runtime complexity property allows CABF to cull the modules faster. The aggregating stage of CABF will reduce the subsequent search space of this floorplanner, and the variable order aggregation enables CABF to search for the best near-optimal solution. Based on Gigascale Systems Research Center and Microelectronics Center of North Carolina circuit benchmarks, CABF gives better optimal solutions and faster runtimes for floorplanning problems involving 9 to 600 modules. This has established that CABF is performing well in respect of reliability and scalability. Besides, CABF shows its potential to be implemented in VLSI physical design as the runtime of CABF is faster with a near-optimal outcome as compared to the other existing algorithms.

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An enhanced perturbing algorithm for floorplan design using the O-tree representation

Cited by 58 publications

References 5 publications

Combinatorial techniques for mixed-size placement

Combinatorial techniques for mixed-size placement

TCG: a transitive closure graph-based representation for non-slicing floorplans

Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

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