An efficient Jacobi-like algorithm for parallel eigenvalue computation

Götze, J.; Paul, Steffen; Sauer, Matthias

doi:10.1109/12.241595

Cited by 72 publications

(40 citation statements)

References 16 publications

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“…Both use rotation mode of CORDIC during the row and column updates. Additionally, diagonal CPs calculate the angle θ given in (9) and distribute it to the off-diagonal CPs on the same row and column. Note that θ in (9) is nothing else but half the angle of 2×1 vector (P qq− P pp ) 2P pq T .…”

Section: Cordic Processors and Systolic Arraymentioning

confidence: 99%

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FPGA based eigenfiltering for real-time portfolio risk analysis

Torun

Yılmaz

Akansu

2013

2013 IEEE International Conference on Acoustics, Speech and Signal Processing

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The empirical correlation matrix of asset returns in an investment portfolio has its built-in noise due to market microstructure. This noise is usually eigenfiltered for robust risk analysis and management. Jacobi algorithm (JA) has been a popular eigensolver method due to its stability and efficient implementations. We present a fast FPGA implementation of parallel JA for noise filtering of empirical correlation matrix. Proposed FPGA implementation is compared with CPU and GPU implementations. It is shown that FPGA implementation of eigenfiltering operator in real-time significantly outperforms the others. We expect to see such emerging high performance DSP technologies to be widely used by the financial sector for real-time risk management and other tasks in the coming years.

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Section: Cordic Processors and Systolic Arraymentioning

confidence: 99%

“…Several VLSI [7][8][9] and FPGA [10][11][12][13] implementations of parallel Jacobi algorithm (PJA) are reported in the literature. Most hardware implementations of Jacobi are put on processors that employ coordinate rotation digital computer (CORDIC) [14,15], i.e.…”

Section: Fpga Based Implementation Of Jacobi Algorithmmentioning

confidence: 99%

FPGA based eigenfiltering for real-time portfolio risk analysis

Torun

Yılmaz

Akansu

2013

2013 IEEE International Conference on Acoustics, Speech and Signal Processing

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“…A few schemes proposed for implementing fast rotations [17,18] constitute approximate digital signal processing [19]. Several applications like computation of Eigen values [18], symmetric Eigen Value Decomposition (EVD) [20], image transformation [21] and high performance filtering [22,23] The proposed scheme and the pipelined architecture are explained in Section 2. Section 3 presents the evaluation of the n bit proposed architecture to derive the expressions for latency and hardware, followed by performance comparison.…”

Section: Introductionmentioning

confidence: 99%

Low latency pipelined CORDIC-like rotator architecture

Boppana

Dhar

2016

International Journal of Electronics

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This work presents an FPGA prototyping of a new low latency pipelined CORDIC-like rotator. The proposed rotator predicts the directions for all rotations in parallel and determines the final coordinates using the architecture with logarithmic relation between the number stages and precision of the target angle. The functionality of the pipelined CORDIC-like rotator is verified by implementing on the Xilinx Virtex-4 pro device (XC4vlx40, 90 nm technology). Based on detailed comparisons with the available pipelined rotators for the resolution of 8 to 12 bits, it is observed that proposed rotator requires less hardware and improves latency by 45% to 85%.

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“…In this paper, we selected the Jacobi EVD method as a typical iterative algorithm since the convergence of this methodology is very robust to modification of the processor elements (Brent and Luk, 1985;Gotze et al, 1993;Goetze and Hekstra, 1995;Klauke and Goetze, 2001). We have investigated the influences in DSM design with different sizes of multiprocessor arrays (i.e., 4×4, 16×16 and 25×25).…”

Section: Introductionmentioning

confidence: 99%

A VLSI design concept for parallel iterative algorithms

Sun

Götze

2009

Adv. Radio Sci.

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Abstract. Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array) in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors) usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified µ-rotation CORDIC architecture.

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An efficient Jacobi-like algorithm for parallel eigenvalue computation

Cited by 72 publications

References 16 publications

FPGA based eigenfiltering for real-time portfolio risk analysis

FPGA based eigenfiltering for real-time portfolio risk analysis

Low latency pipelined CORDIC-like rotator architecture

A VLSI design concept for parallel iterative algorithms

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