An automatic temperature compensation of internal sense ground for subquarter micron DRAM's

Ooishi, T.; Komiya, Yuichiro; Hamade, K.; Asakura, M.; Yasuda, Katsuhiro; Furutani, K.; Hidaka, Hideto; Miyata, Hiroshi; Ozaki, H.

doi:10.1109/4.375968

Cited by 3 publications

(1 citation statement)

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“…Process/device modifications such as a lightly doped source/drain region (to reduce the current gain of the parasitic bipolar transistor and the impact ionization near the drain) [29] and the use of a pMOS cell transistor (lower impact ionization rate and current gain for the parasitic pnp transistor) [30] have been explored. One very effective circuit technique is the boosted sense-ground (BSG) scheme [31]- [33], where the "low" bit-line level is raised (to, say, 0.5 V) above the unselected word-line level to suppress the subthreshold leakage by the negative of the cell transistor. The BSG scheme has been found very effective in improving the dynamic retention time of an SOI DRAM ( Fig.…”

Section: Dynamic Random Access Memoriesmentioning

confidence: 99%

SOI for digital CMOS VLSI: design considerations and advances

Chuang

Anderson

1998

Proc. IEEE

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This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAM's), dynamic random access memories (DRAM's), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed. The use of smart-body contact to improve the power and delay performance is discussed, as are global design issues.

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Section: Dynamic Random Access Memoriesmentioning

confidence: 99%