An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements

Online clock skew tuning for timing speculation

“…With the help of TDB designs, the authors of [11] proposed a post-silicon clock timing adjustment strategy, but how to program the tunable elements and determine their locations is not addressed. In [10,12], the authors combined a statistical timing driven skew scheduling algorithm with a post-silicon clock tuning scheme.…”

“…Earlier works in this domain [1][2][3][4][5] try to find a good clock schedule that maximizes the timing slack of all paths. Recently, with the introduction of tunable clock tree to combat process variation [9], researchers have also presented various post-silicon clock skew tuning techniques to improve circuit timing performance [6,8,[10][11][12].…”

A study on placement of post silicon clock tuning buffers for mitigating impact of process variation

“…The tuning process used in this paper, is described in [21]. It is an algorithmic process based on Critical Path Tracing (CPT) [19][20] [21].…”

“…It is an algorithmic process based on Critical Path Tracing (CPT) [19][20] [21]. For the sake of brevity, the details are omitted here.…”

“…The tuning target selection steps are described in [21]. It is the starting point for the clock-tree synthesis described in this paper.…”