Proceedings of the 43rd Annual Conference on Design Automation - DAC '06 2006
DOI: 10.1145/1146909.1146948
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An automated, reconfigurable, low-power RFID tag

Abstract: This paper describes an ultra low power active RFID tag and its automated design flow. RFID primitives to be supported by the tag are enumerated with RFID macros and the behavior of each primitive is specified using ANSI-C within the template to automatically generate the tag controller. Two power saving components, a passive transceiver/burst switch and a smart buffer, are presented to save power and increase tag lifetime. Based on a test program, the processors required 183, 43, and 19 µJ per transaction for… Show more

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Cited by 19 publications
(4 citation statements)
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“…StrongARM, ESIC and Xscale are the three low-power embedded microprocessor which prototype the design Also an Actel Fusion, Xilinx Coolrunner II and direct ASIC implementation are the three hardware controller which are considered. [1] A paper by Jianping Wang Huiyun Li and Fengqi Yu in 2007 presented the design of RDIF tag based on a new structure as well as in this design, they focuses on the security issue and a new technique was proposed based on hash-lock structure. This makes the tag more secure than the non-security based tags.…”
Section: Literature Reviewmentioning
confidence: 99%
See 1 more Smart Citation
“…StrongARM, ESIC and Xscale are the three low-power embedded microprocessor which prototype the design Also an Actel Fusion, Xilinx Coolrunner II and direct ASIC implementation are the three hardware controller which are considered. [1] A paper by Jianping Wang Huiyun Li and Fengqi Yu in 2007 presented the design of RDIF tag based on a new structure as well as in this design, they focuses on the security issue and a new technique was proposed based on hash-lock structure. This makes the tag more secure than the non-security based tags.…”
Section: Literature Reviewmentioning
confidence: 99%
“…However, passive tags require less maintenance than active tags. [1] Basically, the design of the RFID tag consists of two partsanalog front end and digital back end. The analog front end is responsible for the modulation and demodulation of the and the digital back end is responsible for the data processing such as instruction decoding and storage usually with the ROM.…”
Section: Introductionmentioning
confidence: 99%
“…The receiver, which is kept active to react to an inquiry from the interrogator, therefore determines the shelf life of an active RFID tag. To further reduce the power of the RFID tag receiver two main technologies have been proposed: (1) a passive transceiver or burst switch allowing the tag to remain in a sleep mode until activated with RF energy; and (2) a smart buffer, which allows the controller to remain asleep while an incoming packet is buffered [ 18 ]. Use of RFID as the wake-up radio channel has been shown to provide a viable solution due to the low cost and ready off-the-shelf availability of RFID [ 19 ].…”
Section: Hardware Implementation Considerationsmentioning
confidence: 99%
“…The final result of this automation flow is an actual RFID device prototype. The technique has been demonstrated produce several RFID tag prototypes using microprocessors, FPGAs, and ASICs in [38][39][40]. While this approach only (a) Template generated from the RFID parser.…”
Section: Cto Hdl Translationmentioning
confidence: 99%