An architectural overview of the programmable multimedia processor, TM-1

Rathnam, S.; Slavenburg, G.

doi:10.1109/cmpcon.1996.501790

Cited by 74 publications

(28 citation statements)

References 8 publications

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“…The analog-to-digital and digital-toanalog converters are implemented as separate tiles in our multiprocessor system. The actors v CD and v SD are executed on a TM2270 which belongs to the TriMedia family [11]. We refer to this processor as the Digital Signal Processor (DSP).…”

Section: Methodsmentioning

confidence: 99%

Cache aware mapping of streaming applications on a multiprocessor system-on-chip

Moonen

Bekooij

Berg

et al. 2008

Proceedings of the Conference on Design, Automation and Test in Europe

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Section: Methodsmentioning

confidence: 99%

Cache aware mapping of streaming applications on a multiprocessor system-on-chip

Moonen

Bekooij

Berg

et al. 2008

Proceedings of the Conference on Design, Automation and Test in Europe

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“…Camposano and Wilberg used the approach for designing application-specific VLIW architectures for low-speed video algorithms [2]. Rathnam and Slavenbrug used the approach for the design of the TriMedia programmable multi-media processor TM1 [14]. For DSP processors, the approach has been used byZivojnović et al [16].…”

Section: : Related Workmentioning

confidence: 99%

An approach for quantitative analysis of application-specific dataflow architectures

Kienhuis

Deprettere

Vissers

et al.

Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors

174

101

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In this paper we present an approach for quantitative analysis of application-specific dataflow architectures. The approach allows the designer to rate design alternatives in a quantitative 1: IntroductionIn the application domain of real-time video, the required processing power is in the order of hundreds of Risc-like operations per pixel, while the data rate of pixel streams is in the range of 10 to 100 Msamples per second. Consequently architectures are needed that perform billions of operations per second and have an internal communication bandwidth of Gbytes per second.In the application domain of real-time video we focus on dedicated architectures that support the concept of streams [17] and achieve the required performance by exploiting the inherent parallelism of the applications on domain-specific, coarse-grain processors, with limited internal flexibility (i.e. weakly programmable). An example of such a domain-specific architecture is given in figure 1. The architecture consists of different dedicated application-specific coarse-grain processors that operate independently of each other on data-streams. These streams are exchanged between the coarse-grain processors via a communication network and is controlled by some global controller. These kinds of architectures are typically embedded in a larger system that also contains memory and a general purpose processor, e.g. a Risc processor.In the design of these architectures, many choices have to be made. In this paper we present a simulation environment that aids the designer in making these choices based on quantitative information. In section 2 we present our problem statement. A solution approach is given in section 3. In section 4 we review related work of quantitative evaluation of design alternatives. The solution approach is further detailed for application-specific dataflow architectures in the following sections. In

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“…There are three main features of multimedia processors [2], [10], [11] that may impact the performance of motion estimation. They are: 1) wider data path compared with general purpose processors; 2) subword parallel architecture (SWP) to deal with multiple pixels simultaneously; and 3) special instructions for SAD calculation.…”

Section: B Considerations For Multimedia Processorsmentioning

confidence: 99%

Predictive line search: an efficient motion estimation algorithm for MPEG-4 encoding systems on multimedia processors

Huang¹,

Ma²,

Shen³

et al. 2003

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-This paper describes an efficient motion-estimation algorithm, the predictive line search (PLS), for real-time implementations of MPEG-4 encoder on multimedia processors. The motion-vector predictor is used as the starting point in the search process because the correlation between neighboring motion vectors is strong. The line search pattern is used in the proposed algorithm to reduce the memory access as well as to exploit the special multimedia processor instructions for sum of absolute difference calculations. Experimental results show that the performance of the PLS is very close to that of the full-search (FS) algorithm. Compared with the well-known diamond search and one-dimensional FS, the PLS shows better performance and robustness, especially for high motion sequences. A prototype MPEG-4 encoding system is implemented on a 216-MHz multimedia processor with very long instruction word architecture to verify the effectiveness of the PLS. Real-time encoding of MPEG-4 Simple Profile Level 3 (CIF, 30 fps) can be achieved with only 57% of the processor load.

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An architectural overview of the programmable multimedia processor, TM-1

Cited by 74 publications

References 8 publications

Cache aware mapping of streaming applications on a multiprocessor system-on-chip

Cache aware mapping of streaming applications on a multiprocessor system-on-chip

An approach for quantitative analysis of application-specific dataflow architectures

Predictive line search: an efficient motion estimation algorithm for MPEG-4 encoding systems on multimedia processors

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