An analytical delay model for RLC interconnects

Kahng, Andrew B.; Muddu, S.

doi:10.1109/43.664231

Cited by 209 publications

(121 citation statements)

References 21 publications

Supporting

Mentioning

119

Contrasting

Order By: Relevance

“…For each sink we compute the delay and slew using SPICE simulator and measure the relative error of the appropriate metric to the SPICE result. The simulation goal is twofold: first, to compute our delay metric (WbD) with Kahng-Muddu Model (KM) [9] and Elmore Delay (ED [1] and second, to assess our slew metric (WbS) in comparison to [1] and [11]. We call these metrics as ES and BkS, respectively.…”

Section: Resultsmentioning

confidence: 99%

Delay and Slew Metrics for On-Chip VLSI Interconnect

Kar¹,

Chattaraj²,

Chandra³

et al. 2010

IJCEE

View full text Add to dashboard Cite

Section: Resultsmentioning

confidence: 99%

Delay and Slew Metrics for On-Chip VLSI Interconnect

Kar¹,

Chattaraj²,

Chandra³

et al. 2010

IJCEE

View full text Add to dashboard Cite

“…There is a large literature on Elmore delay and related topics; see, e.g., Alpert et al (2001a), Kashyap et al (2004), Kahng and Muddu (1997), Gupta et al (1997), Schevon (1995), andHorowitz (1984). Rubenstein et al (1983) published the simple closed-form formula described above for computing the mean of the impulse response of RC interconnect trees.…”

Section: Rc Tree Optimizationmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

153

146

View full text Add to dashboard Cite

This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

show abstract

“…Elmore delay model uses the first circuit moment which can not capture the effect of inductance of interconnect, to estimate the delay and the accuracy would be deteriorated when clock frequency increases. To achieve higher accuracy, a two-pole model which based on RLC interconnects is presented by Kahng and Muddu [2]. The model based on the first two moments, gains higher accuracy than previous ones due to the second moment capturing the effect of inductance.…”

Section: Introductionmentioning

confidence: 99%

A delay model for interconnect trees based on ABCD matrix

Zhou

Jin

et al. 2008

2008 Asia and South Pacific Design Automation Conference

View full text Add to dashboard Cite

-The accuracy of interconnect delay estimations can be improved by the method presented in this paper in which the first two moments are obtained with ABCD matrix and a stable model to incorporate effects of transport delay into the delay estimate is developed. Simulation results show that the method share the same accuracy with traditional methods when rise time delay is much longer than transport delay and more accurate when the two are of the same order. I IntroductionElmore delay model based on RC network, still is one of the most popular interconnect delay estimation tools for circuit synthesis and optimization as well as post layout circuit verification, due to its simplicity, recursive properties and ease of adaptation to VLSI interconnect [1]. Elmore delay model uses the first circuit moment which can not capture the effect of inductance of interconnect, to estimate the delay and the accuracy would be deteriorated when clock frequency increases. To achieve higher accuracy, a two-pole model which based on RLC interconnects is presented by Kahng and Muddu[2]. The model based on the first two moments, gains higher accuracy than previous ones due to the second moment capturing the effect of inductance.The transmission line in network of the previous models would cut into several segments and replaced with RC or RLC circuits. However, replacing segments with lumped RC or RLC circuits would lead approximation error to calculate the moments. In the paper, transmission line would be replaced with ABCD matrix which can describe the line accurately. And the accuracy of moment calculation would be improved compared to those previous works. Furthermore, the transport delay is ignored in previous models. Therefore, in this paper, the total delay is divided into the transport delay and the rise time delay. The transport delay must be calculated first and remove its impact from the original system. Then, a stable RLC model is used to approximate the new system to estimate the rise time delay. II. Background A. Interconnect tree analysis with ABCD matrixIn Kahng's works, each segment of interconnects is modeled as equivalent RLC circuits. The interconnect trees would be replaced with the RLC network. The first moment and the second moment of transfer function from the source to the sink can be easily figured out by iterative formulas [2]. The accuracy of models is mainly dependent on what the number of segment the interconnect lines are cut into. In the paper, each interconnect line is modeled with ABCD matrix. As we all know, the ABCD matrix of interconnects which derive from telegraphy equations can described interconnect accurately.For an arbitrary interconnect tree, we consider the main path between the source and the sink of interest, and replace each subtree with its respective admittance. To calculate the response at the sink we replace the interconnect line on the main path with ABCD matrix. Fig. 1 shows an example of a main path where every branch on the main path of the tree is replaced with ABCD matr...

show abstract

An analytical delay model for RLC interconnects

Cited by 209 publications

References 21 publications

Delay and Slew Metrics for On-Chip VLSI Interconnect

Delay and Slew Metrics for On-Chip VLSI Interconnect

Digital Circuit Optimization via Geometric Programming

A delay model for interconnect trees based on ABCD matrix

Contact Info

Product

Resources

About