An 88-way multiprocessor within an FPGA with customizable instructions

Hoare, Raymond R.; Tung, Shenchih; Werger, Katrina Jean-Marie

doi:10.1109/ipdps.2004.1303325

Cited by 6 publications

(5 citation statements)

References 7 publications

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“…Hence, given enough bandwidth of the bus interconnect, the processing inside the CPUs is performed in parallel with accessing the memory and thus the term T ovh is also divided by N. If these assumptions do not hold and the interconnect is the bottleneck causing non-negligible delays, then the following is true in the general case: (9) where T par_ovh represents the synchronization overheads.…”

Section: Speedup With Coprocessor Acceleratorsmentioning

confidence: 99%

See 1 more Smart Citation

On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable Platforms

Kornaros

Motakis

2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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Instruction set accelerator architectures have emerged recently as light-weight hardware coprocessors, so as to transparently improve applications performance. This paper investigates the effectiveness of adding hardware accelerators as refers to scaling, based on applications that show data level parallelism such as image edge detection and fractal applications. The implementation results using reconfigurable technology show that, by utilizing a number of hardware coprocessor units, applications such as Sobel edge detection can achieve speedup more than 37 . Finally, architectural directions based on the developed case studies show that even better performance can be achieved when the overheads of communication, of serialized data accesses, shared memory and of bus protocols are reduced.

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Section: Speedup With Coprocessor Acceleratorsmentioning

confidence: 99%

“…In [9] a multiprocessor on FPGA is presented with a central instruction stream feeding 88 processing elements. While in [10] Svensson shows a reconfigurable coprocessor with coarse-grained datapath processing elements which utilizes a local memory system.…”

Section: Introductionmentioning

confidence: 99%

On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable Platforms

Kornaros

Motakis

2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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“…Another FPGA-based SIMD processor is described in [11]. This processor is implemented in an Altera Stratix EP1S80 FPGA, has 88 8-bit PEs, and can operate at a maximum clock speed of 121 MHz.…”

Section: Related Workmentioning

confidence: 99%

A Prototype Multithreaded Associative SIMD Processor

Schaffer

Walker

2007

2007 IEEE International Parallel and Distributed Processing Symposium

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The performance of SIMD processors is often limited by the time it takes to transfer data between the centralized control unit and the parallel processor array. This is especially true of hybrid SIMD models, such as associative computing, that make extensive use of global search operations. Pipelining instruction broadcast can help, but is not enough to solve the problem, especially for massively parallel processors with thousands of processing elements. In this paper, we describe a SIMD processor architecture that combines a fully pipelined broadcast/reduction network with hardware multithreading to reduce performance degradation as the number of processors is scaled up.

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“…NIOS-2 and OpenRISC offer the facility to add custom instructions [Oliv04], with options to choose cache size and bit-width [Altni02], [Open08]. It is possible to instantiate several softcores on the same FPGA to create a multiple processor array with custom interfacing logic [Hoar04]. Altera [Altni02], appear to be de-emphasising their embedded ARM core and instead are promoting the NIOS-2 as a more flexible alternative.…”

Section: Reconfigurable Computing Architecturesmentioning

confidence: 99%

Wire level encapsulation framework for increasing FPGA design productivity

Oliver¹

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This thesis explores the performance impact of optimising the components of a Field Programmable Gate Array (FPGA) system down to the lowest level independently from other parts of the system. The motivation for this is that not only is the design and verification effort put in to a component reused, the optimisation effort expended in mapping, placement and routing is also reused. FPGA technology has its roots in digital circuit design and, like every silicon technology, it advances every 18 months, doubling the gate capacity available to the designer. The single largest threat to this growth is the gap that is forming between the number of available gates and the ability of designers to use these gates in the time frame of a typical design cycle. The design gap is more acutely felt in the FPGA computing community since the main perceived strength of FPGA technology is its reconfigurability. As an example, High Performance Computing (HPC) on FPGA offers a clear advantage. However, designer productivity issues are a major threat to its wide spread use. HPC is achieved on FPGA by specialising the architecture. Specialisation implies a design process. Thus, designer productivity is the main restricting factor to increasing the computing functionality that FPGA systems can offer. Reuse is recognised as a powerful approach to improving designer productivity. In the field of software design, reuse of third party software code is possible with both the static linking of pre-compiled libraries, and the dynamic linking of libraries during run-time. Even in the realms of Application Specific Integrated Circuit (ASIC) design, pre-placed and routed "hard" macros are available from third parties. However, currently implemented third party reuse schemes for FPGA design operate at either the source code or the net-list level. The full spectrum of compromises between flexibility and compositional effort have not been explored in previous works. Pre-routed FPGA components represent a reuse strategy that presents very low system composition effort at the cost of very little component flexibility. It is relatively simple to constrain component resource to regions on the surface of an FPGA device. The greater challenge lies in applying constraints on the interconnect usage of each component without adversely affecting system performance. There has been little work done to investigate the proposition of the third party reuse of pre-routed FPGA components. In order to investigate the feasibility of pre-routed FPGA components, a detailed structural model generator for FPGA architectures has been developed along with a complimentary set of design automation tools. The elements of an FPGA architecture and automated tool behaviour affected by component encapsulation are identified. This leads to a design methodology, including modified tools, facilitating the automated mapping of components to an encapsulated region of FPGA resource and interconnect without interference from any other mapped region. The methodology supports automated con...

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An 88-way multiprocessor within an FPGA with customizable instructions

Cited by 6 publications

References 7 publications

On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable Platforms

On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable Platforms

A Prototype Multithreaded Associative SIMD Processor

Wire level encapsulation framework for increasing FPGA design productivity

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