An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer

Kawai, S.; Aoyama, Hiromitsu; Ito, Ryoko; Shimizu, Yutaka; Ashida, Mitsuyuki; Maki, Asuka; Takeuchi, Tomohiko; Kobayashi, Hiroyuki; Urakawa, Go; Hoshino, H.; Saigusa, Shigehito; Koyama, Kazushi; Morita, Makoto; Nihei, Ryuichi; Goto, Daisuke; Nagata, Motoki; Nakata, Kengo; Ikeuchi, Katsuyoshi; Yoshioka, Kentaro; Tachibana, Ryoichi; Arai, Makoto; Teh, Chen-Kong; Suzuki, Atsushi; Yoshida, Hiroshi; Hagiwara, Yosuke; Kato, Takayuki; Seto, I.; Horiguchi, T.; Ban, Kanako; Takahashi, Kyosuke; Kajihara, Hirotsugu; Yamagishi, T.; Fujimura, Y.; Horiuchi, Kazuhisa; Nonin, Katsuya; Kurose, Kengo; Yamada, Hideki; Taniguchi, Koichi; Sekiya, Masahiro; Tomizawa, Takeshi; Taki, Daisuke; Ikuta, Masaaki; Suzuki, Tomoya; Ando, Yuki; Yashima, Daisuke; Kaihotsu, Takahisa; Mori, Hiroki; Nakanishi, Koichi; Kumagaya, Takeshi; Unekawa, Yasuo; Aoki, Tsuguhide; Onizuka, Kohei; Mitomo, Toshiya

doi:10.1109/isscc.2018.8310374

Cited by 13 publications

(9 citation statements)

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“…These approaches impose several challenges to silicon design. The 1024-QAM demands extreme I/Q balance over a wide frequency range up to 80 MHz to achieve at least −35 dB EVM or less [30]. Some experimental results with high-order modulation at different signal bandwidths of DVB-C2 and NHK have also been published [31]- [33].…”

Section: Performance Comparsionmentioning

confidence: 99%

A 67-86 GHz Spectrum-Efficient CMOS Transmitter Supporting 1024-QAM With a Process-Variation-Tolerant Design

et al. 2020

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This paper describes a direct-conversion E-band transmitter (TX) in 65-nm CMOS. To demonstrate the feasibility of E-band 1024-quadrature amplitude modulation (QAM), a 67 to 86 GHz direct-conversion CMOS transmitter with broadband image rejection is presented. The transmitter contains an I (in-phase) and Q (quadrature-phase) modulator and a five-stage power amplifier. To achieve a 40 dBc image-rejection ratio (IRR) of the I/Q modulator for E-band, a broadband half-quadrature generator (HQG), which contains a composite right/left-handed (CRLH) based divider, quadrature couplers, and baluns is proposed. For the purpose of minimizing the phase imbalance, phase balance lines are utilized in HQG to achieve a 1-degree phase accuracy under different tuning lines. Subsequently, the reflection can be mitigated by optimizing the impedance matching between the HQG and the mixer core. Meanwhile, because millimeter-wave (MMW) circuits are susceptible to process variations, a process-variation-tolerant design is introduced to mitigate IRR variation, especially under 40 dBc. The transmitter demonstrates a measured flat conversion gain (CG) of 23 ± 2 dB from 56 to 86 GHz. The proposed TX achieves an IRR better than 40 dBc from 67 to 86 GHz (bandwidth of 19 GHz) with a peak IRR of 56.2 dBc at 70 GHz. Furthermore, the proposed TX has exhibited a 6 bit/s/Hz spectral efficiency with 1024-QAM under the orthogonal frequency-division multiplexing (OFDM) modulation format. The 1.129 mm 2 E-band TX achieves a measured output power of 6.5 dBm with a total dc power consumption of 164 mW from a 1.2 V supply voltage. INDEX TERMS CMOS, E-band, half-quadrature generator (HQG), image-rejection ratio (IRR), millimeter-wave (MMW) integrated circuit, process-variation-tolerant design, transmitter (TX), 1024-quadrature amplitude modulation (QAM).

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Section: Performance Comparsionmentioning

confidence: 99%

A 67-86 GHz Spectrum-Efficient CMOS Transmitter Supporting 1024-QAM With a Process-Variation-Tolerant Design

et al. 2020

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“…The devices of 802.11ax are designed to operate in existing 2.4-and 5-GHz spectrums, requiring a dual-band transceiver. In the literatures and commercial products, two separate radio frequency (RF) transceiver channels are used different operating frequencies and integrated together to enable 2.4-/5-GHz dual band operation [4]- [9]. There are two major issues when the wideband LPF is designed.…”

Section: Introductionmentioning

confidence: 99%

A 3^rd/5^th Order Active RC Chebyshev Analog Baseband Low-Pass Filter With Reconfigurable Bandwidth and Gain

Wang

Huang

2021

IEEE Access

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The design of 3 rd /5 th order active RC Chebyshev low-pass filter (LPF) with reconfigurable bandwidth and gain is based on 55 nm CMOS technology. The filter is integrated into draft IEEE 802.11ax concurrent dual band four antenna transceiver analog baseband circuit. Programmable capacitor bank of the filter is used to adjust bandwidth. The typical bandwidth of receiving filter is 10/20/40 MHz, and that of transmitting filter is 12/24/50 MHz. Adjust the gain ranging from -10 to 18 dB in passband by programmable resistor bank. The current consumption of typical bandwidth of receiving filter is 2.08 mA at a 1.5 V supply and has properties of 10 MHz bandwidth (BW), 36 dB gain, -62 dBm input signal, -39 dB third intermodulation distortion (IMD3), 17.1 nV/√Hz equivalent input noise (EIN). As for transmitting filter, the current consumption of typical bandwidth is 1.25 mA at a 1.5 V supply and has the properties of 10 MHz BW, -6 dB gain, 0 dBm input signal, -38 dB IMD3, 75 nV/√Hz EIN. Area of the whole filter is 0.08 mm 2 . INDEX TERMS Active RC, analog baseband, low-pass filter.

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“…Significant work has been done to support up to 80-MHz 802.11ac/ax [2]- [6]. In recent years, several architectures supporting contiguous or noncontiguous 80 + 80-MHz 802.11ac/ax are also reported [7]- [10]. In other words, this frequency combination is a new kind of CA employed by 802.11ac/ax [11]- [13].…”

Section: Introductionmentioning

confidence: 99%

“…In contrast to LTE-A, the 5-GHz-frequency bands are more concentrated and the available BW is larger. One straightforward approach to realize CA receiver is to employ several parallel direct-conversion paths [7]- [9], [14]- [17]. While it achieves a good tradeoff among power, noise, and linearity, this architecture is prone to local oscillator (LO) pulling, especially when working at intra-band mode.…”

Section: Introductionmentioning

confidence: 99%

A Parallel Sliding-IF Receiver Front-End With Sub-2-dB Noise Figure for 5–6-GHz WLAN Carrier Aggregation

Yang

Boon

et al. 2021

IEEE J. Solid-State Circuits

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This article presents a parallel sliding-IF 5-6-GHz wireless local area network (WLAN) receiver front-end supporting two-band carrier aggregation (CA), which alleviates potential local oscillator (LO) pulling and crosstalk problems. The supported frequency spacing between any two different carriers ranges from tens to hundreds of MHz. First, a complementary current-reused single-ended LNA with very low noise figure (NF) is developed to guarantee a low noise performance. Second, an active balun-splitter establishes a bridge between the LNA and the following parallel fully differential downconversion paths. Next, to optimize the performance of the passive double-conversion mixer, a detailed analysis has been conducted and shown that the time offset with specific values between the two LOs maximizes conversion gain and minimizes noise contribution, which enhances harmonic rejection simultaneously. Fabricated in 65-nm CMOS technology, this receiver front-end achieves an average 1.9-dB NF with a 39-dB gain at 5-6 GHz for single-carrier scenario, degraded by 0.4 dB with 35-dB gain for two-band CA scenario. It consumes 35 and 60 mA with 1.2-V supply for single carrier and two-band CA scenario, respectively. The total area is 0.56 mm 2 .

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An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer

Cited by 13 publications

References 1 publication

A 67-86 GHz Spectrum-Efficient CMOS Transmitter Supporting 1024-QAM With a Process-Variation-Tolerant Design

A 67-86 GHz Spectrum-Efficient CMOS Transmitter Supporting 1024-QAM With a Process-Variation-Tolerant Design

A 3^rd/5^th Order Active RC Chebyshev Analog Baseband Low-Pass Filter With Reconfigurable Bandwidth and Gain

A Parallel Sliding-IF Receiver Front-End With Sub-2-dB Noise Figure for 5–6-GHz WLAN Carrier Aggregation

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An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer

Cited by 13 publications

References 1 publication

A 67-86 GHz Spectrum-Efficient CMOS Transmitter Supporting 1024-QAM With a Process-Variation-Tolerant Design

A 67-86 GHz Spectrum-Efficient CMOS Transmitter Supporting 1024-QAM With a Process-Variation-Tolerant Design

A 3rd/5th Order Active RC Chebyshev Analog Baseband Low-Pass Filter With Reconfigurable Bandwidth and Gain

A Parallel Sliding-IF Receiver Front-End With Sub-2-dB Noise Figure for 5–6-GHz WLAN Carrier Aggregation

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A 3^rd/5^th Order Active RC Chebyshev Analog Baseband Low-Pass Filter With Reconfigurable Bandwidth and Gain